VisualSim
provides a graphical modeling and simulation environment to select buses
and networks for new applications, and designing new and emerging bus standards.
VisualSim provides a complete list of Buses and
Network standards. These bus models have been validated and are
in production use at a number of companies worldwide. The user can vary the
bus block parameters and add pre-defined VisualSim blocks to configure
the full system model. Customers have used the VisualSim environment for
designing complex systems using PCIe, AXI and CoreConnect. Semiconductor
companies have been designed new network-onpchip and other proprietary high-performance buses.
The
VisualSim model associated with this description is provided below.
You can view, change parameter values and run simulation right from
within the Web Browser. No additional software is required. This
shows how you can use a pre-built VisualSim model for doing trade-studies.
To use the models at the links,
click on the GO button to run the simulation. Double-click on any parameter in
the model window to change the parameter value.
Click
here to view and execute the VisualSim
model
Custom arbitrations such as Round-Robin,
partitioning of large and complex application prior to implementation.
No software code or RTL (Verilog/VHDL) is required to conduct this analysis.
The architecture can be partitioned to meet a target application based on
profile and performance metrics. Experiments by customers have shown accuracy
of over 90% with this VisualSim approach. Moreover, this analysis is done prior
to any implementation. Hence the rework cost is almost fully eliminated. This
example shows the application of this transaction modeling approach to a complex
wireless and multimedia application containing audio, video and high-speed data
transfer applications in a single device.
Introduction
New bus architectures are being
developed, such as 3GIO (INTEL),
HyperTransport (AMD), etc., to improve
bus throughput and reduce bus latency,
as microprocessor and memory speeds
outpace older bus design throughput
and latency, such as PCI. The demo
focuses on building a switch-based
bus in VisualSim to evaluate overall
throughput and latency for a single
four port switch configuration.
