Mirabilis Design - VisualSim Processor and Peripheral Modeling Toolkit

VisualSim Processor and Peripheral Modeling Toolkit

Processor Generators

Single- and multi-core on SoC

Processor on board

SMID and MIMD

VLIW and RISC

Application-specific

Peripheral Generators

Profile-based software task generator

Cache

Memory: SDRAM, SRAM, DRAM and Flash

Memory Controller: SDR, DDR, DDR2, DDR3, RDRAM and Flash

Disk Drive

Vendors Supported

For all other vendors, please contact Mirabilis Design (Email) for more details.

Purpose

Architecture trade-off to select the right platform to meet performance and power metrics.
Explore future technologies for scaleability and anticipated requirements

Application

Select the processor and peripherals including cache hierarchy
Optimize the application distribution for performance and power on multi-core systems
New processsor architectures

Generated Statistics

Latency per task or thread
Utilization and throughput of processor resources (Registers, I Cache, D Cache and Execution Units) and peripherals
Instantaneous and average power consumed by processor and peripherals
Advanced statistics such as hit-ratio, thread activity, memory consumed per requester, buffer occupancy, context switching time and stall time

Figure 1: VisualSim Architecture Model of a Platform

VisualSim Processor and Peripheral Modeling Toolkit enables users to create processor models for performance anlysis and architecture exploration. Current generation Instruction Set Simulators offer very little visibility into the processor internals- a huge requirements for both Processor Architects and software designers. These processor mdoels are fully customizable through parameters. For example, modifying the second level cache from an internal to an external cache to a SDRAM is a matter of changing a single parameter value. Current virtual prototyping solutions require 6-9 months of custom services to create a specific processor model, has limited architecture flexibility and significant startup cost. Using the VisualSim processor Toolkit, engineers can create a model of a processor within 4 (four) hours.

This graphical Instruction Set Simulator (ISS) combines performance and power information. The processor model is generated from a spreadsheet containing parameters that describe the resources (cache and Execution Units), pipeline and instruction set. The generated processor model can be combined with peripheral and system resources to define a network of servers, SoC or a Single Board Computer. Software code or models of proposed software can be executed on this processor platform to generate various statistics. The ISS model provides complete visibility into the pipeline, memory and execution unit processing.

The activities during the pipeline can be customized to specific implementation. These can extend from buffered store operation to co-processor calls from the pipeline. The models can be used to experiment with cache strategies, branch prediction algorithm, off-load engines, software allocation schemes and processor selection.

This processor ISS will be cycle- and instruction- accurate and will be provide reports for both cycle-count and power consumption/ energy dissipation. The graphical ISS is constructed using information that is normally available in the product datasheet. The processor can handle hazard modeling, pipeline flushes, custom branch algorithms, pipeline stalls, context-switching, interrupt instructions and load-store operations.

Over 250 standard and custom statistics generators are embedded into the generators. The appropriate statistics on one or all components can be generated on the fly. The activity plot showing the activity of all the internal and peripheral resources can be launched in real-time for testing functional correctness, resource consumption and timing accuracy. Typical statistics will include utilization, stall time, context switching, hit-ratios, throughput, task delay, latency and idle-time.

This technology radically reduces the time it now takes architects and engineers to create electronic system level (ESL) models. With the VisualSim Processor and Peripheral Library, a user can create processor, instruction set, cache, memory, and bus models for commercial and new custom processors. A software developer can validate assumptions, thread distributions and best load scheduling techniques in a very short period of time, even before the code development has commenced.