ARM AMBA AHB Bus Matrix

AMBA-AHB Multilayer Bus matrix with self-Motivated Arbitration scheme

AMBA Interface

  • ARM AMBA AHB/APB
    Advanced High Performance bus (AHB) and AMBA Advanced Peripheral Bus (APB) to connect with processors and IP
  • ARM AMBA AHB Bus Matrix
    AMBA-AHB Multilayer Bus matrix with self-motivated arbitration scheme
  • ARM AMBA AXI/ACP
    AMBA Advanced eXtensible Interface (AXI) point-to-point bus
  • ARM AMBA CoreLink CMN-600
    CoreLink CMN-600 Coherent Mesh Network designed for extremely high data transfer
  • ARM AMBA CHI5
    AMBA 5 CHI network for high-frequency, non-blocking data

Quick Explanation

  • The bus matrix module, BusMatrix, enables multiple AHB masters from different AHB buses to be connected to multiple AHB slaves on multiple AHB slave buses. It enables parallel access to a number of shared AHB slaves from a number of different AHB masters. The bus matrix determines the master that gains access to each slave, and routes the control signals and data signals between them. This block is required in multi-layer AHB systems.

Protocol

  • ARM AMBA AHB
  • ARM AMBA APB
  • Bus Matrix

Model Link

Introduction

Advanced Peripheral Bus (APB) is designed for low bandwidth control accesses, like register interfaces on system peripherals. This bus has an address and data phase similar to AHB, but a much reduced, low complexity signal list. The Advanced High performance Bus (AHB) is also a bus protocol introduced by ARM. It has larger bus widths compared to the previous releases. AHB is capable of waits, errors and bursts.

Overview

This library provides a system-level modelling implementation of the AMBA 2 and the updated AMBA 3 specification from ARM. This library supports the AHB, AHB-lite, multi-layer AHB and APB. The blocks are completely flexible and can be configured for almost any topology. The blocks can be connected to hardware components, accelerators or custom-programmed blocks- SystemC or using the VisualSim graphical environment. Using these components, the user can assemble, configure, simulate, debug and analyse the power consumption and performance of the next-generation SoC. The performance attributes and the various power modes of the AHB/APB embedded in the library block. The library contains a number of traffic models that have been pre-built and parameterized to simulate dynamic system operations

Parameters Used

The library contains over 20 application templates that provides detailed examples of usage along with different ARM processors, Network-on-Chip (NoC), memory controllers, DDR, accelerators, bridges, crossbars, media devices, Wi-Fi and I/Os. The reports and statistics provide detailed report on activity per connected node, read and write latency, utilization, throughput and buffer activity. Some of the parameters used in AMBA APB/AHB are as follows:

  • Bus_Speed_Mhz: Speed of the bus
  • Burst_Size_Bytes: Determines the maximum length of the transaction
  • FIFO_Buffers: Size of the buffer at each master or slave
  • FCFS- First-Come First-Serve
  • Round_Robin_Port_Array: Order of each master and slave port for the Round Robin arbitration
  • Devices connected via each port
  • Split and Retry

Features

The model, containing the AHB/APB can accept an Excel spreadsheet to define the traffic sequences. Some of the key features of VisualSim AMBA AHB model are as follows:

  • Single edge clock protocol
  • Split transactions
  • Multiple bus masters and slaves
  • Burst transfers
  • Retry transactions
  • Wait states
  • Single outstanding transaction
  • Pipelined address phase operations
  • Single-cycle bus master handover
  • Large bus widths
  • AHB Bus Matrix

Library Components:

  • AHB
  • APB
  • Bridge

AHB Bus Matrix - Implements Microcontroller Architecture