AMBA Advanced eXtensible Interface (AXI) point-to-point Bus
VisualSim AMBA AXI/ACE Interconnect bus is a system-level architecture exploration, topology validation and arbitration protocol validation platform for SoC. This is an exact implementation of the AMBA 3.0 interconnect specification standard but abstracted to a transaction-level and runs at 1000X the speed of other commercially available models. The library provides all the building blocks required for the instantiation of a complete SoC. Unlike current SoC solution, the internal details of the AXI bus is provided inan unencrypted and in human-readable form. This includes all the Master-Slave ports, internal buffers, crossbars, port logic, arbiters, and interfaces. The block has been parameterized for performance attributes such as speed, buffers, traffic management, internal architecture, and arbitration algorithm selection. As the block is completely user-readable, any aspect can be easily modified. This includes the crossbar structure and the arbitration algorithms. The library also contains the interfaces between AXI and AHB, PCI, PCIe, Ethernet and SRIO.
Some of the parameters supported in AXI bus including low-latency, high-performance, pipelined operation, multi-layer, integration of custom controllers, interleaved Read/Write operations, timing isolation from the rest of the system, resizing the number of Masters and Slaves, supports unlimited number of Masters and Slaves, variable data widths, variable block size and separate clock on each interface port. The AXI can also support priority and pre-emption scheduling. The interfaces and the crossbar can support multiple data sizes.
The AMBA_AXI Bus protocol is targeted at high performance, high frequency system designs and includes a number of features that makes it suitable for a high-speed sub-micron inter-connect. The objectives of AMBA_AXI bus are to be suitable for high-bandwidth and low latency designs and enable high frequency operations without using complex bridges. It meets the interface requirements of a wide range of components and it is suitable for memory controllers with high initial access latency and provide flexibility in the implementation of interconnect architectures.A critical advantage of the VisualSim AXI bus is that an ISS/cycle-accurate model with the OS and the compiled is not required to test the topology. Using the VisualSim core Architecture library, the processor and the instruction sequence of a software task can be emulated and the read/write on the bus can be modelled. The user can input the traffic profiles in a Excel spread sheet.
Advanced eXtensible Interface (AXI). The third generation of AMBA interface defined in the AMBA 3 specification, is targeted at high performance, high clock frequency system designs and includes features that make it suitable for high speed sub-micrometer interconnect. AXI Coherency Extensions (ACE), is defined as part of the AMBA 4 specification, extends AXI with additional signalling introducing system wide coherency. This system coherency allows multiple processors to share memory and enables technology like ARM’s big.Little processing.