R4

Used for a encryption algorithm where the packet is decrypted and the data is filtered using a TI DSP C64x

ARM Processor Family

  • Cortex M0 Microcontroller
    Coming Soon
  • Cortex M3 Microcontroller
    Using the standard M3 library product to construct a SoC controller for an IoT application
  • Cortex M4 Microcontrollers
    Using the standard M4 library product to construct a SoC controller for an IoT application
  • A7
    Dual ARM A7 executing AES code. Code was generated from the ARM Emulator
  • A8
    Single ARM A8 Cortex implements an AES code. Includes power analysis, throughput, pipeline utilization and task latency
  • A9
    Dual ARM Cortex A9 with a PCI interface sending traffic
  • A53
    Modeling tasks on the A53 including loading and storing using a DMA
  • A72
    Coming Soon
  • A76
    Coming Soon
  • R4
    Used for a encryption algorithm where the packet is decrypted and the data is filtered using a TI DSP C64x

ARM8_R4_Platform_w_Programmable_MPMC2

Browsable image of the model.

  • To download OpenWebStart click on the links -
    Windows- Compatibility:Windows 10 or higher (*)
    macOS - Compatibility:macOS 10.15 (Catalina) or higher (*)
    Linux - Compatibility:Ubuntu 18.04 LTS or higher (*)
  • For an executable version,
  • Mouse over the icons to view parameters. Click on hierarchy and plotters to reveal content (if provided).
  • To simulate, click on Launch button, open downloaded file and click Run on the Java Security Page.
ARM8_R4_Platform_w_Programmable_MPMC2model <h2>MPMC_SDRAM2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Sim_Time</td><td>Sim_Time /*Sim_Time*/</td><td>6.0E-4</td></tr><tr><td>MPMC_Speed_Mhz</td><td>MPMC_Speed_Mhz</td><td>600.0</td></tr><tr><td>MPMC_Pipeline_Slots</td><td>MPMC_Pipeline_Slots</td><td>4</td></tr><tr><td>MPMC_Width_Bytes</td><td>MPMC_Byte_Width</td><td>8</td></tr><tr><td>MPMC_Plotting_Destination</td><td>&quot;MyPlot&quot; /* &quot;none&quot; turns off */</td><td>&quot;MyPlot&quot;</td></tr></table> <h2>Instruction_Set</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Instruction_Set_Name</td><td>&quot;ARM8_INSTR&quot;</td><td>&quot;ARM8_INSTR&quot;</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;Instruction_Set</td><td>ProcessorGenerator-&gt;Instruction_Set</td></tr><tr><td>Instruction_Set_Text</td><td>/* Instruction Set : Reference ARM8-Cortex pdf. */\\n\\n Mnew Arg1 Arg2 Arg3 ; /* Label */\\n ARM8 INT_1 ; /* ARM execution unit */\\n\\nbegin INT_1 ;\\n\\n ART_ADD 1 4 ; /* group ARITHMETIC */\\n last_round_add 1 ;\\n ART_ADC 1 4 ;\\n ART_SUB 1 4 ;\\n ART_SBC 1 4 ;\\n ART_RSB 1 4 ;\\n ART_RSC 1 4 ;\\n ART_MUL 2 3 ;\\n ART_MLA 2 3 ;\\n ART_MULS 4 ;\\n ART_MLAS 4 ;\\n ART_UMULL 3 4 ;\\n ART_UMLAL 3 4 ;\\n ART_SMULL 3 4 ;\\n ART_SMLAL 3 4 ;\\n ART_UMULLS 5 ;\\n ART_UMLALS 5 ;\\n ART_SMULLS 5 ;\\n ART_SMLALS 5 ;\\n ART_CMP 1 4 ;\\n ART_CMN 1 4 ;\\n ART_QADD 1 2 ;\\n ART_QSUB 1 2 ;\\n ART_SMULXY 1 ;\\n ART_SMULAXY 2 ;\\n ART_SMULWX 1 ;\\n ART_SMULAWX 2 ;\\n ART_SMULALX 2 3 ;\\n ART_CLZ 1 ;\\n\\n LGL_TST 1 4 ; /* group LOGICAL */\\n LGL_TEQ 1 4 ;\\n LGL_AND 1 4 ;\\n eor 1 ;\\n LGL_ORR 1 4 ;\\n LGL_BIC 1 4 ;\\n\\n BR_B 3 ; /* group LOGICAL */\\n BR_BL 3 ; \\n BR_BX 3 ;\\n BR_BLX 3 ;\\n\\n ldr 1 ; /* group LOAD */\\n lsr 1 ;\\n ldr_rcon 1 ;\\n LD_LDRT 1 5 ; \\n LD_LDRB 1 5 ; \\n LD_LDRBT 1 5 ; \\n LD_LDRSB 1 5 ; \\n LD_LDRH 1 5 ; \\n LD_LDRSH 1 5 ; \\n LD_LDM_PC 5 ; \\n LD_LDM 1 12 ; /* number of registers */\\n\\n STR_STR 1 ; /* group STORE */\\n STR_STRT 1 ; \\n STR_STRB 1 ; \\n STR_STRBT 1 ; \\n STR_STRH 1 ;\\n STR_STM_PC 1 2 ;\\n STR_STM 1 12 ; /* number of registers */\\n\\n MISC_SWP 3 ; /* group MISCELLANEOUS */\\n MISC_SWI 3 ; \\n MISC_BKPT 3 ; \\n\\nend INT_1 ;</td><td>/* Instruction Set : Reference ARM8-Cortex pdf. */\\n\\n Mnew Arg1 Arg2 Arg3 ; /* Label */\\n ARM8 INT_1 ; /* ARM execution unit */\\n\\nbegin INT_1 ;\\n\\n ART_ADD 1 4 ; /* group ARITHMETIC */\\n last_round_add 1 ;\\n ART_ADC 1 4 ;\\n ART_SUB 1 4 ;\\n ART_SBC 1 4 ;\\n ART_RSB 1 4 ;\\n ART_RSC 1 4 ;\\n ART_MUL 2 3 ;\\n ART_MLA 2 3 ;\\n ART_MULS 4 ;\\n ART_MLAS 4 ;\\n ART_UMULL 3 4 ;\\n ART_UMLAL 3 4 ;\\n ART_SMULL 3 4 ;\\n ART_SMLAL 3 4 ;\\n ART_UMULLS 5 ;\\n ART_UMLALS 5 ;\\n ART_SMULLS 5 ;\\n ART_SMLALS 5 ;\\n ART_CMP 1 4 ;\\n ART_CMN 1 4 ;\\n ART_QADD 1 2 ;\\n ART_QSUB 1 2 ;\\n ART_SMULXY 1 ;\\n ART_SMULAXY 2 ;\\n ART_SMULWX 1 ;\\n ART_SMULAWX 2 ;\\n ART_SMULALX 2 3 ;\\n ART_CLZ 1 ;\\n\\n LGL_TST 1 4 ; /* group LOGICAL */\\n LGL_TEQ 1 4 ;\\n LGL_AND 1 4 ;\\n eor 1 ;\\n LGL_ORR 1 4 ;\\n LGL_BIC 1 4 ;\\n\\n BR_B 3 ; /* group LOGICAL */\\n BR_BL 3 ; \\n BR_BX 3 ;\\n BR_BLX 3 ;\\n\\n ldr 1 ; /* group LOAD */\\n lsr 1 ;\\n ldr_rcon 1 ;\\n LD_LDRT 1 5 ; \\n LD_LDRB 1 5 ; \\n LD_LDRBT 1 5 ; \\n LD_LDRSB 1 5 ; \\n LD_LDRH 1 5 ; \\n LD_LDRSH 1 5 ; \\n LD_LDM_PC 5 ; \\n LD_LDM 1 12 ; /* number of registers */\\n\\n STR_STR 1 ; /* group STORE */\\n STR_STRT 1 ; \\n STR_STRB 1 ; \\n STR_STRBT 1 ; \\n STR_STRH 1 ;\\n STR_STM_PC 1 2 ;\\n STR_STM 1 12 ; /* number of registers */\\n\\n MISC_SWP 3 ; /* group MISCELLANEOUS */\\n MISC_SWI 3 ; \\n MISC_BKPT 3 ; \\n\\nend INT_1 ;</td></tr><tr><td>Record_Set_Name</td><td>&quot;Record_Set&quot;</td><td>&quot;Record_Set&quot;</td></tr></table> <h2>Trans_Monitor2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>These blocks fragment and defragment based on parameter settings:\\n\\n</td><td>These blocks fragment and defragment based on parameter settings:\\n\\n</td></tr><tr><td>Block_Name</td><td>&quot;Monitor_2&quot;</td><td>&quot;Monitor_2&quot;</td></tr><tr><td>Optional_Parameters</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value \\nPath none \\nRead_File none \\nSelf_Start false \\nParam_Script none \\nListen_to_File none \\nDuplicate_Input true \\nProfile 0 \\nProfile_File none \\nMaximum_Loops 1000000 \\nBlock_Reference Block_Name \\nPort_Order_Array {&quot;input&quot;} \\n</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value \\nPath none \\nRead_File none \\nSelf_Start false \\nParam_Script none \\nListen_to_File none \\nDuplicate_Input true \\nProfile 0 \\nProfile_File none \\nMaximum_Loops 1000000 \\nBlock_Reference Block_Name \\nPort_Order_Array {&quot;input&quot;} \\n</td></tr><tr><td>Self_Start</td><td>true</td><td>true</td></tr><tr><td>Plotting_Destination</td><td>Monitor_Name</td><td>&quot;MyMonitor&quot;</td></tr><tr><td>Left_to_Right_Sources</td><td>{&quot;DMA_Controller_2&quot;}</td><td>{&quot;DMA_Controller_2&quot;}</td></tr><tr><td>Right_to_Left_Sources</td><td>{&quot;SDRAM_1&quot;}</td><td>{&quot;SDRAM_1&quot;}</td></tr><tr><td>Speed_Mhz</td><td>400.0</td><td>400.0</td></tr></table> <h2>Trans_Monitor</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>These blocks fragment and defragment based on parameter settings:\\n\\n</td><td>These blocks fragment and defragment based on parameter settings:\\n\\n</td></tr><tr><td>Block_Name</td><td>&quot;Monitor_1&quot;</td><td>&quot;Monitor_1&quot;</td></tr><tr><td>Optional_Parameters</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value \\nPath none \\nRead_File none \\nSelf_Start false \\nParam_Script none \\nListen_to_File none \\nDuplicate_Input true \\nProfile 0 \\nProfile_File none \\nMaximum_Loops 1000000 \\nBlock_Reference Block_Name \\nPort_Order_Array {&quot;input&quot;} \\n</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value \\nPath none \\nRead_File none \\nSelf_Start false \\nParam_Script none \\nListen_to_File none \\nDuplicate_Input true \\nProfile 0 \\nProfile_File none \\nMaximum_Loops 1000000 \\nBlock_Reference Block_Name \\nPort_Order_Array {&quot;input&quot;} \\n</td></tr><tr><td>Self_Start</td><td>true</td><td>true</td></tr><tr><td>Plotting_Destination</td><td>Monitor_Name</td><td>&quot;MyMonitor&quot;</td></tr><tr><td>Left_to_Right_Sources</td><td>{&quot;DMA_Controller_1&quot;}</td><td>{&quot;DMA_Controller_1&quot;}</td></tr><tr><td>Right_to_Left_Sources</td><td>{&quot;SDRAM_1&quot;}</td><td>{&quot;SDRAM_1&quot;}</td></tr><tr><td>Speed_Mhz</td><td>400.0</td><td>400.0</td></tr></table> <h2>Trans_Monitor4</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>These blocks fragment and defragment based on parameter settings:\\n\\n</td><td>These blocks fragment and defragment based on parameter settings:\\n\\n</td></tr><tr><td>Block_Name</td><td>&quot;Monitor_4&quot;</td><td>&quot;Monitor_4&quot;</td></tr><tr><td>Optional_Parameters</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value \\nPath none \\nRead_File none \\nSelf_Start false \\nParam_Script none \\nListen_to_File none \\nDuplicate_Input true \\nProfile 0 \\nProfile_File none \\nMaximum_Loops 1000000 \\nBlock_Reference Block_Name \\nPort_Order_Array {&quot;input&quot;} \\n</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value \\nPath none \\nRead_File none \\nSelf_Start false \\nParam_Script none \\nListen_to_File none \\nDuplicate_Input true \\nProfile 0 \\nProfile_File none \\nMaximum_Loops 1000000 \\nBlock_Reference Block_Name \\nPort_Order_Array {&quot;input&quot;} \\n</td></tr><tr><td>Self_Start</td><td>true</td><td>true</td></tr><tr><td>Plotting_Destination</td><td>Monitor_Name</td><td>&quot;MyMonitor&quot;</td></tr><tr><td>Left_to_Right_Sources</td><td>{&quot;e405_1&quot;}</td><td>{&quot;e405_1&quot;}</td></tr><tr><td>Right_to_Left_Sources</td><td>{&quot;SDRAM_1&quot;}</td><td>{&quot;SDRAM_1&quot;}</td></tr><tr><td>Speed_Mhz</td><td>400.0</td><td>400.0</td></tr></table> <h2>Trans_Monitor3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>These blocks fragment and defragment based on parameter settings:\\n\\n</td><td>These blocks fragment and defragment based on parameter settings:\\n\\n</td></tr><tr><td>Block_Name</td><td>&quot;Monitor_3&quot;</td><td>&quot;Monitor_3&quot;</td></tr><tr><td>Optional_Parameters</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value \\nPath none \\nRead_File none \\nSelf_Start false \\nParam_Script none \\nListen_to_File none \\nDuplicate_Input true \\nProfile 0 \\nProfile_File none \\nMaximum_Loops 1000000 \\nBlock_Reference Block_Name \\nPort_Order_Array {&quot;input&quot;} \\n</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value \\nPath none \\nRead_File none \\nSelf_Start false \\nParam_Script none \\nListen_to_File none \\nDuplicate_Input true \\nProfile 0 \\nProfile_File none \\nMaximum_Loops 1000000 \\nBlock_Reference Block_Name \\nPort_Order_Array {&quot;input&quot;} \\n</td></tr><tr><td>Self_Start</td><td>true</td><td>true</td></tr><tr><td>Plotting_Destination</td><td>Monitor_Name</td><td>&quot;MyMonitor&quot;</td></tr><tr><td>Left_to_Right_Sources</td><td>{&quot;e405_1&quot;}</td><td>{&quot;e405_1&quot;}</td></tr><tr><td>Right_to_Left_Sources</td><td>{&quot;SDRAM_1&quot;}</td><td>{&quot;SDRAM_1&quot;}</td></tr><tr><td>Speed_Mhz</td><td>400.0</td><td>400.0</td></tr></table> <h2>DS_xTime_yData_Plotter</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>fillOnWrapup</td><td>true</td><td>true</td></tr><tr><td>legend</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>startingDataset</td><td>0</td><td>0</td></tr><tr><td>fileName</td><td>Enter Filename to save plot</td><td>&quot;Enter Filename to save plot&quot;</td></tr><tr><td>Field_Trace_Name</td><td>Plot_Name</td><td>&quot;Plot_Name&quot;</td></tr><tr><td>Field_Y_Value</td><td>input.Plot_Value</td><td>&quot;input.Plot_Value&quot;</td></tr><tr><td>Field_Color</td><td>Plot_Color</td><td>&quot;Plot_Color&quot;</td></tr><tr><td>Field_Offset</td><td>Plot_Offset</td><td>&quot;Plot_Offset&quot;</td></tr><tr><td>viewPlot</td><td>true</td><td>true</td></tr><tr><td>savePlot</td><td>false</td><td>false</td></tr></table> <h2>IN</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Destination_Name</td><td>MyMonitor</td><td>&quot;MyMonitor&quot;</td></tr><tr><td>Destination_Type</td><td>Global</td><td>Global</td></tr></table> <h2>SDRAM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Memory_Name</td><td>SDRAM_Name</td><td>&quot;SDRAM_1&quot;</td></tr><tr><td>Memory_Speed_Mhz</td><td>MPMC_Speed_Mhz</td><td>600.0</td></tr><tr><td>Memory_Size_MBytes</td><td>SDRAM_MBytes</td><td>1000.0</td></tr><tr><td>Access_Time</td><td>&quot;Read 2.0, Prefetch 1.8, Write 1.8, ReadWrite 1.8, Erase 1.8&quot;</td><td>&quot;Read 2.0, Prefetch 1.8, Write 1.8, ReadWrite 1.8, Erase 1.8&quot;</td></tr><tr><td>FIFO_Buffers</td><td>SDRAM_FIFO_Buffers</td><td>32</td></tr><tr><td>Refresh_Rate_Cycles</td><td>16384000</td><td>16384000</td></tr><tr><td>Refresh_Cycles</td><td>16</td><td>16</td></tr><tr><td>Memory_Address</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td></tr><tr><td>Controller_Time</td><td>&quot;Cycle_Time&quot;</td><td>&quot;Cycle_Time&quot;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Width_Bytes</td><td>8</td><td>8</td></tr><tr><td>Memory_Type</td><td>DDR2</td><td>DDR2</td></tr></table> <h2>PCI_Traffic</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>inter_time</td><td>500.0/33.0e6</td><td>1.5151515151515E-5</td></tr></table> <h2>Ethernet_traffic</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>inter_time</td><td>500.0/100.0e6</td><td>5.0E-6</td></tr></table> <h2>uEngine_Script</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>uEngine_Name</td><td>&quot;uEngine_Name&quot;</td><td>&quot;uEngine_Name&quot;</td></tr><tr><td>Input_Priority_Field</td><td>&quot;Field_Name_or_None&quot;</td><td>&quot;Field_Name_or_None&quot;</td></tr><tr><td>Max_Queue_Length</td><td>64</td><td>64</td></tr><tr><td>Time_Mode</td><td>Relative_Time</td><td>Relative_Time</td></tr><tr><td>Destination_Type</td><td>Local</td><td>Local</td></tr></table> <h2>SingleEvent</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>_explanation</td><td>Source-&gt;Event-&gt;SingleEvent\t</td><td>Source-&gt;Event-&gt;SingleEvent\t</td></tr><tr><td>time</td><td>0.0</td><td>0.0</td></tr><tr><td>value</td><td>0.0</td><td>0.0</td></tr></table> <h2>Boolean_Trigger</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Port_Arrival_Order</td><td>Input_or_Control_First</td><td>Input_or_Control_First</td></tr></table> <h2>Latency</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>fillOnWrapup</td><td>true</td><td>true</td></tr><tr><td>legend</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>startingDataset</td><td>0</td><td>0</td></tr><tr><td>fileName</td><td>Enter Filename to save plot</td><td>&quot;Enter Filename to save plot&quot;</td></tr><tr><td>viewPlot</td><td>true</td><td>true</td></tr><tr><td>savePlot</td><td>false</td><td>false</td></tr></table> <h2>If_Else2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>If_Statement</td><td>&quot;A_Destination != FPGA_Name &amp;&amp; A_Destination != Architecture_Name&quot;</td><td>&quot;A_Destination != FPGA_Name &amp;&amp; A_Destination != Architecture_Name&quot;</td></tr><tr><td>If_Execute</td><td>&quot;1, 2&quot;</td><td>&quot;1, 2&quot;</td></tr><tr><td>Else_Execute</td><td>&quot;3, 4&quot;</td><td>&quot;3, 4&quot;</td></tr><tr><td>Field_Statement_1</td><td>Name_X Assign Name_Y OP Name_Z</td><td>&quot;Name_X Assign Name_Y OP Name_Z&quot;</td></tr><tr><td>Field_Statement_2</td><td>Name_X Assign Name_Y OP Name_Z</td><td>&quot;Name_X Assign Name_Y OP Name_Z&quot;</td></tr><tr><td>Field_Statement_3</td><td>Name_X Assign Name_Y OP Name_Z</td><td>&quot;Name_X Assign Name_Y OP Name_Z&quot;</td></tr><tr><td>Field_Statement_4</td><td>Name_X Assign Name_Y OP Name_Z</td><td>&quot;Name_X Assign Name_Y OP Name_Z&quot;</td></tr><tr><td>Random_Seed</td><td>123457L</td><td>123457L</td></tr></table> <h2>If_Else</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>If_Statement</td><td>&quot;A_Destination != FPGA_Name &amp;&amp; A_Destination != Architecture_Name&quot;</td><td>&quot;A_Destination != FPGA_Name &amp;&amp; A_Destination != Architecture_Name&quot;</td></tr><tr><td>If_Execute</td><td>&quot;1, 2&quot;</td><td>&quot;1, 2&quot;</td></tr><tr><td>Else_Execute</td><td>&quot;3, 4&quot;</td><td>&quot;3, 4&quot;</td></tr><tr><td>Field_Statement_1</td><td>Name_X Assign Name_Y OP Name_Z</td><td>&quot;Name_X Assign Name_Y OP Name_Z&quot;</td></tr><tr><td>Field_Statement_2</td><td>Name_X Assign Name_Y OP Name_Z</td><td>&quot;Name_X Assign Name_Y OP Name_Z&quot;</td></tr><tr><td>Field_Statement_3</td><td>Name_X Assign Name_Y OP Name_Z</td><td>&quot;Name_X Assign Name_Y OP Name_Z&quot;</td></tr><tr><td>Field_Statement_4</td><td>Name_X Assign Name_Y OP Name_Z</td><td>&quot;Name_X Assign Name_Y OP Name_Z&quot;</td></tr><tr><td>Random_Seed</td><td>123457L</td><td>123457L</td></tr></table> <h2>Expr_If_Else</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_A</td><td>Result_A = input.tag ==4 ? true:false</td><td>&quot;Result_A = input.tag ==4 ? true:false&quot;</td></tr><tr><td>Expression_B</td><td>Latency = Result_A==true?TNow:Latency</td><td>&quot;Latency = Result_A==true?TNow:Latency&quot;</td></tr><tr><td>Expression_C</td><td>Result_C = MyRegExpression_C_or_None</td><td>&quot;Result_C = MyRegExpression_C_or_None&quot;</td></tr><tr><td>Expression_D</td><td>Result_D = MyRegExpression_D_or_None</td><td>&quot;Result_D = MyRegExpression_D_or_None&quot;</td></tr><tr><td>Output_Ports</td><td>output_true, output_false</td><td>&quot;output_true, output_false&quot;</td></tr><tr><td>Output_Results</td><td>input, input</td><td>&quot;input, input&quot;</td></tr><tr><td>Output_Conditionals</td><td>Result_A, !Result_A</td><td>&quot;Result_A, !Result_A&quot;</td></tr></table> <h2>Database2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>*.xml, *.csv files abs or rel (./) path\\n -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n -- match_all.field not allowed</td><td>*.xml, *.csv files abs or rel (./) path\\n -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n -- match_all.field not allowed</td></tr><tr><td>Linking_Name</td><td>&quot;MyDatabase_2&quot;</td><td>&quot;MyDatabase_2&quot;</td></tr><tr><td>fileOrURL</td><td>&nbsp;</td><td>&quot;&quot;</td></tr><tr><td>Data_Structure_Text</td><td>A_Task_Name\tA_Instruction\tA_IDX\tA_Task_Source\tBurst_Word_Size\tA_Task_Address A_Address_Min\tA_Address_Max\tA_Command\tA_Bytes\tA_Priority\tA_Destination \\nMyTask2 ADD\t 0\tSDRAM_1\t 32\t 1 0\t 0\t Read\t 32\t0\t DMA_Controller_2 \\n\\n</td><td>A_Task_Name\tA_Instruction\tA_IDX\tA_Task_Source\tBurst_Word_Size\tA_Task_Address A_Address_Min\tA_Address_Max\tA_Command\tA_Bytes\tA_Priority\tA_Destination \\nMyTask2 ADD\t 0\tSDRAM_1\t 32\t 1 0\t 0\t Read\t 32\t0\t DMA_Controller_2 \\n\\n</td></tr><tr><td>Input_Fields</td><td>&quot;ID&quot;</td><td>&quot;ID&quot;</td></tr><tr><td>Lookup_Fields</td><td>&quot;ID&quot;</td><td>&quot;ID&quot;</td></tr><tr><td>Output_Expression</td><td>&quot;output = match&quot; /* FORMAT output = match.fieldb */</td><td>&quot;output = match&quot;</td></tr><tr><td>Mode</td><td>Read</td><td>Read</td></tr></table> <h2>I_O2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>IO_Name</td><td>&quot;IO_D1&quot;</td><td>&quot;IO_D1&quot;</td></tr><tr><td>IO_Destination</td><td>&quot;Fld_Name_or_String&quot;</td><td>&quot;Fld_Name_or_String&quot;</td></tr><tr><td>IO_Command</td><td>&quot;Fld_Name_or_String&quot;</td><td>&quot;Fld_Name_or_String&quot;</td></tr><tr><td>IO_Instruction</td><td>&quot;Fld_Name_or_String_or_None&quot;</td><td>&quot;Fld_Name_or_String_or_None&quot;</td></tr><tr><td>IO_Bytes</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr><tr><td>IO_Priority</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr><tr><td>IO_Address</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr></table> <h2>I_O</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>IO_Name</td><td>&quot;IO_I1&quot;</td><td>&quot;IO_I1&quot;</td></tr><tr><td>IO_Destination</td><td>&quot;Fld_Name_or_String&quot;</td><td>&quot;Fld_Name_or_String&quot;</td></tr><tr><td>IO_Command</td><td>&quot;Fld_Name_or_String&quot;</td><td>&quot;Fld_Name_or_String&quot;</td></tr><tr><td>IO_Instruction</td><td>&quot;Fld_Name_or_String_or_None&quot;</td><td>&quot;Fld_Name_or_String_or_None&quot;</td></tr><tr><td>IO_Bytes</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr><tr><td>IO_Priority</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr><tr><td>IO_Address</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr></table> <h2>Database</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>*.xml, *.csv files abs or rel (./) path\\n -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n -- match_all.field not allowed</td><td>*.xml, *.csv files abs or rel (./) path\\n -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n -- match_all.field not allowed</td></tr><tr><td>Linking_Name</td><td>&quot;MyDatabase_1&quot;</td><td>&quot;MyDatabase_1&quot;</td></tr><tr><td>fileOrURL</td><td>&nbsp;</td><td>&quot;&quot;</td></tr><tr><td>Data_Structure_Text</td><td>A_Task_Name\tA_Instruction\tA_IDX\tA_Task_Source\tBurst_Word_Size\tA_Task_Address A_Address_Min\tA_Address_Max\tA_Command\tA_Bytes\tA_Priority\tA_Destination \\nMyTask\t ADD\t 0\tSDRAM_1\t 32\t 1 0\t 0\t Read\t 32\t0\t DMA_Controller_1 \\nMyTask2 ADD\t 0\tSDRAM_1\t 32\t 2 0\t 0\t Read\t 32\t0\t DMA_Controller_2 \\n\\n</td><td>A_Task_Name\tA_Instruction\tA_IDX\tA_Task_Source\tBurst_Word_Size\tA_Task_Address A_Address_Min\tA_Address_Max\tA_Command\tA_Bytes\tA_Priority\tA_Destination \\nMyTask\t ADD\t 0\tSDRAM_1\t 32\t 1 0\t 0\t Read\t 32\t0\t DMA_Controller_1 \\nMyTask2 ADD\t 0\tSDRAM_1\t 32\t 2 0\t 0\t Read\t 32\t0\t DMA_Controller_2 \\n\\n</td></tr><tr><td>Input_Fields</td><td>&quot;ID&quot;</td><td>&quot;ID&quot;</td></tr><tr><td>Lookup_Fields</td><td>&quot;ID&quot;</td><td>&quot;ID&quot;</td></tr><tr><td>Output_Expression</td><td>&quot;output = match&quot; /* FORMAT output = match.fieldb */</td><td>&quot;output = match&quot;</td></tr><tr><td>Mode</td><td>Read</td><td>Read</td></tr></table> <h2>Local_Link2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>IO_Controller_Name</td><td>&quot;Local_Link_2&quot;</td><td>&quot;Local_Link_2&quot;</td></tr><tr><td>Control_to_Device_Cycles</td><td>1</td><td>&quot;1&quot;</td></tr><tr><td>Control_to_Device_Address</td><td>DS_Fld_Name_or_Integer</td><td>&quot;DS_Fld_Name_or_Integer&quot;</td></tr><tr><td>Device_to_Control_Cycles</td><td>1</td><td>&quot;1&quot;</td></tr><tr><td>FIFO_Buffers</td><td>4</td><td>&quot;4&quot;</td></tr><tr><td>Speed_Mhz</td><td>100.0</td><td>&quot;100.0&quot;</td></tr><tr><td>Control_to_Device_Mode</td><td>Custom</td><td>Custom</td></tr><tr><td>Address_Mode</td><td>No</td><td>No</td></tr></table> <h2>Local_Link</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>IO_Controller_Name</td><td>&quot;Local_Link_1&quot;</td><td>&quot;Local_Link_1&quot;</td></tr><tr><td>Control_to_Device_Cycles</td><td>1</td><td>&quot;1&quot;</td></tr><tr><td>Control_to_Device_Address</td><td>DS_Fld_Name_or_Integer</td><td>&quot;DS_Fld_Name_or_Integer&quot;</td></tr><tr><td>Device_to_Control_Cycles</td><td>1</td><td>&quot;1&quot;</td></tr><tr><td>FIFO_Buffers</td><td>4</td><td>&quot;4&quot;</td></tr><tr><td>Speed_Mhz</td><td>100.0</td><td>&quot;100.0&quot;</td></tr><tr><td>Control_to_Device_Mode</td><td>Custom</td><td>Custom</td></tr><tr><td>Address_Mode</td><td>No</td><td>No</td></tr></table> <h2>DMA_Controller2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>DMA_Controller_Name</td><td>&quot;DMA_Controller_2&quot;</td><td>&quot;DMA_Controller_2&quot;</td></tr><tr><td>Memory_Database_Reference</td><td>&quot;MyDatabase_2&quot;</td><td>&quot;MyDatabase_2&quot;</td></tr><tr><td>DMA_to_Device_Cycles</td><td>1</td><td>&quot;1&quot;</td></tr><tr><td>DMA_to_Device_Address</td><td>DS_Fld_Name_or_Integer</td><td>&quot;DS_Fld_Name_or_Integer&quot;</td></tr><tr><td>Device_to_DMA_Cycles</td><td>none</td><td>&quot;none&quot;</td></tr><tr><td>Channel_FIFO_Buffers</td><td>16</td><td>&quot;16&quot;</td></tr><tr><td>Speed_Mhz</td><td>100.0</td><td>&quot;100.0&quot;</td></tr><tr><td>DMA_Channels</td><td>3</td><td>3</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Burst_Size_Bytes</td><td>128</td><td>128</td></tr><tr><td>DMA_to_Device_Mode</td><td>Custom</td><td>Custom</td></tr></table> <h2>DMA_Controller</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>DMA_Controller_Name</td><td>&quot;DMA_Controller_1&quot;</td><td>&quot;DMA_Controller_1&quot;</td></tr><tr><td>Memory_Database_Reference</td><td>&quot;MyDatabase_1&quot;</td><td>&quot;MyDatabase_1&quot;</td></tr><tr><td>DMA_to_Device_Cycles</td><td>1</td><td>&quot;1&quot;</td></tr><tr><td>DMA_to_Device_Address</td><td>DS_Fld_Name_or_Integer</td><td>&quot;DS_Fld_Name_or_Integer&quot;</td></tr><tr><td>Device_to_DMA_Cycles</td><td>None</td><td>&quot;None&quot;</td></tr><tr><td>Channel_FIFO_Buffers</td><td>16</td><td>&quot;16&quot;</td></tr><tr><td>Speed_Mhz</td><td>100.0</td><td>&quot;100.0&quot;</td></tr><tr><td>DMA_Channels</td><td>2</td><td>2</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Burst_Size_Bytes</td><td>128</td><td>128</td></tr><tr><td>DMA_to_Device_Mode</td><td>Custom</td><td>Custom</td></tr></table> <h2>Text</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Title</td><td>&quot;Processor Stats&quot;</td><td>&quot;Processor Stats&quot;</td></tr><tr><td>Lines_Buffered</td><td>5</td><td>5</td></tr><tr><td>Rows_Displayed</td><td>20</td><td>20</td></tr><tr><td>Columns_Displayed</td><td>75</td><td>75</td></tr><tr><td>Font_Type</td><td>Lucida Console</td><td>Lucida Console</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr></table> <h2>State_Plot</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Proc_Name</td><td>&quot;ARM8_1&quot;</td><td>&quot;ARM8_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;Bus_1&quot;</td><td>&quot;Bus_1&quot;</td></tr><tr><td>Cache_Name</td><td>&quot;Cache_1&quot;</td><td>&quot;Cache_1&quot;</td></tr><tr><td>DRAM_Name</td><td>&quot;SDRAM_1&quot;</td><td>&quot;SDRAM_1&quot;</td></tr></table> <h2>Arch_Setup2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>FPGA_Name</td><td>&quot;Virtex4&quot;</td></tr><tr><td>Field_Name_Mapping</td><td>/* First row contains Column Names. */\\nExternal_Field_Name Internal_Field_Name ; \\nA_Address A_Address ; \\nA_Bytes A_Bytes ; \\nA_Data A_Data ; \\nA_IDX A_IDX ; \\nA_Instruction A_Instruction ; \\nA_Priority A_Priority ; \\nA_Source A_Source ; \\nA_Destination A_Destination ; \\nA_Task_ID A_Task_ID ; \\nA_Time A_Time ; \\n</td><td>/* First row contains Column Names. */\\nExternal_Field_Name Internal_Field_Name ; \\nA_Address A_Address ; \\nA_Bytes A_Bytes ; \\nA_Data A_Data ; \\nA_IDX A_IDX ; \\nA_Instruction A_Instruction ; \\nA_Priority A_Priority ; \\nA_Source A_Source ; \\nA_Destination A_Destination ; \\nA_Task_ID A_Task_ID ; \\nA_Time A_Time ; \\n</td></tr><tr><td>Routing_Table</td><td>/* First row contains Column Names. */\\nSource_Node Destination_Node Hop Source_Port ;\\nARM8_1\t\tSDRAM_1\t\t SDRAM_1\t bus_out ;\\nSDRAM_1\t \tARM8_1\t\t ARM8_1\t output\t;</td><td>/* First row contains Column Names. */\\nSource_Node Destination_Node Hop Source_Port ;\\nARM8_1\t\tSDRAM_1\t\t SDRAM_1\t bus_out ;\\nSDRAM_1\t \tARM8_1\t\t ARM8_1\t output\t;</td></tr><tr><td>Number_of_Samples</td><td>10</td><td>10</td></tr><tr><td>Statistics_to_Plot</td><td>&quot;405_1_INT_3_Throughput_MIPs_Mean&quot;</td><td>&quot;405_1_INT_3_Throughput_MIPs_Mean&quot;</td></tr><tr><td>Internal_Plot_Trace_Offset</td><td>2</td><td>2</td></tr><tr><td>Listen_to_Architecture_Options</td><td>Pipeline</td><td>Pipeline</td></tr></table> <h2>A8_R4</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>FPGA_Name</td><td>FPGA_Name</td><td>&quot;Virtex4&quot;</td></tr><tr><td>uP_Name</td><td>&quot;ARM8_1&quot;</td><td>&quot;ARM8_1&quot;</td></tr><tr><td>uP_Name_Speed</td><td>600.0</td><td>600.0</td></tr><tr><td>Mem_Name</td><td>SDRAM_Name</td><td>&quot;SDRAM_1&quot;</td></tr><tr><td>I_Cache_KB</td><td>&quot;16&quot;</td><td>&quot;16&quot;</td></tr><tr><td>D_Cache_KB</td><td>&quot;8&quot;</td><td>&quot;8&quot;</td></tr></table> <h2>Arch_Setup</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Field_Name_Mapping</td><td>/* First row contains Column Names. */\\nExternal_Field_Name Internal_Field_Name ; \\nA_Address A_Address ; \\nA_Bytes A_Bytes ; \\nA_Data A_Data ; \\nA_IDX A_IDX ; \\nA_Instruction A_Instruction ; \\nA_Priority A_Priority ; \\nA_Source A_Source ; \\nA_Destination A_Destination ; \\nA_Task_ID A_Task_ID ; \\nA_Time A_Time ; \\n</td><td>/* First row contains Column Names. */\\nExternal_Field_Name Internal_Field_Name ; \\nA_Address A_Address ; \\nA_Bytes A_Bytes ; \\nA_Data A_Data ; \\nA_IDX A_IDX ; \\nA_Instruction A_Instruction ; \\nA_Priority A_Priority ; \\nA_Source A_Source ; \\nA_Destination A_Destination ; \\nA_Task_ID A_Task_ID ; \\nA_Time A_Time ; \\n</td></tr><tr><td>Routing_Table</td><td>/* First row contains Column Names. */\\nSource_Node Destination_Node Hop Source_Port ; \\nLocal_Link_1 SDRAM_1 SDRAM_1 output ;\\nLocal_Link_2 SDRAM_1 SDRAM_1 output ;\\nSDRAM_1 IO_I1 IO_I1 output ;\\nSDRAM_1 IO_D1 IO_D1 output ;\\nSDRAM_1 DMA_Controller_1 DMA_Controller_1 output ;\\nSDRAM_1 DMA_Controller_2 DMA_Controller_2 output ;\\nDMA_Controller_1 IO_3 IO_3 Dout ;\\nDMA_Controller_2 IO_4 IO_4 Dout ;</td><td>/* First row contains Column Names. */\\nSource_Node Destination_Node Hop Source_Port ; \\nLocal_Link_1 SDRAM_1 SDRAM_1 output ;\\nLocal_Link_2 SDRAM_1 SDRAM_1 output ;\\nSDRAM_1 IO_I1 IO_I1 output ;\\nSDRAM_1 IO_D1 IO_D1 output ;\\nSDRAM_1 DMA_Controller_1 DMA_Controller_1 output ;\\nSDRAM_1 DMA_Controller_2 DMA_Controller_2 output ;\\nDMA_Controller_1 IO_3 IO_3 Dout ;\\nDMA_Controller_2 IO_4 IO_4 Dout ;</td></tr><tr><td>Number_of_Samples</td><td>2</td><td>2</td></tr><tr><td>Statistics_to_Plot</td><td>&quot;Processor_1_PROC_Utilization_Min, Processor_1_PROC_Utilization_Mean, Processor_1_PROC_Utilization_Max&quot;</td><td>&quot;Processor_1_PROC_Utilization_Min, Processor_1_PROC_Utilization_Mean, Processor_1_PROC_Utilization_Max&quot;</td></tr><tr><td>Internal_Plot_Trace_Offset</td><td>2</td><td>2</td></tr><tr><td>Listen_to_Architecture_Options</td><td>DRAM</td><td>DRAM</td></tr></table>