Intel ATOM

Modeling a IoT application using an ATOm processor

Processor Family

  • RISC-V SIMD
    RISC_V model execution the NP Benchmark tasks
  • RISC-V MIMD
    Coming Soon
  • PowerPC
    Network processor using a PowerPC. The backplane is a PCIe bus. The Processor, DMA and Switched Ethernet connected to the AXI Bus.
  • Coldfire
    Application of Coldfire in a Electronic Control Unit for a automotive application
  • RAD750
    Implements the ARINC653 Time-Space RTOS running a set of tasks on the basic RAD750 with PCI, 1553B and SpaceWire interfaces.
  • Renesas SH4
    ECU containing a SH4 running safety applications
  • Nvidia
    Drive-PX modeled with a CAN Network that is sending 4 Radar signals and 2 camera signals. The Drive-PX is modeled with the 4 ARM A72, 2 Denver and the GPU
  • SPARC and LEON
    Drive-PX modeled with a CAN Network that is sending 4 Radar signals and 2 camera signals. The Drive-PX is modeled with the 4 ARM A72, 2 Denver and the GPU
  • Intel ATOM
    Modeling a IoT application using an ATOm processor
  • AMD Opteron
    Compares the memory architecture of the Opteron Direct Connect with Xeon Shared Bus
  • TI OMAP
    Uses the OMAP4460 for a camera application

Camera_to_ATOM_2_new

Browsable image of the model.

  • To download OpenWebStart click on the links -
    Windows- Compatibility:Windows 10 or higher (*)
    macOS - Compatibility:macOS 10.15 (Catalina) or higher (*)
    Linux - Compatibility:Ubuntu 18.04 LTS or higher (*)
  • For an executable version,
  • Mouse over the icons to view parameters. Click on hierarchy and plotters to reveal content (if provided).
  • To simulate, click on Launch button, open downloaded file and click Run on the Java Security Page.
Camera_to_ATOM_2_newmodel <h2>Init_Memory</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Memory_Init_Text</td><td>/* Memory Initialize Template \\nName Type Value */\\nPower_Usage\tglobal\t{0.0,0.0,0.0,0.0,0.0};</td><td>/* Memory Initialize Template \\nName Type Value */\\nPower_Usage\tglobal\t{0.0,0.0,0.0,0.0,0.0};</td></tr></table> <h2>DMA_Controller2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>DMA_Controller_Name</td><td>&quot;DMA&quot;</td><td>&quot;DMA&quot;</td></tr><tr><td>Memory_Database_Reference</td><td>&quot;DMADatabase&quot;</td><td>&quot;DMADatabase&quot;</td></tr><tr><td>DMA_to_Device_Cycles</td><td>RegEx_or_None</td><td>&quot;RegEx_or_None&quot;</td></tr><tr><td>DMA_to_Device_Address</td><td>DS_Fld_Name_or_Integer</td><td>&quot;DS_Fld_Name_or_Integer&quot;</td></tr><tr><td>Device_to_DMA_Cycles</td><td>RegEx_or_None</td><td>&quot;RegEx_or_None&quot;</td></tr><tr><td>Channel_FIFO_Buffers</td><td>10</td><td>&quot;10&quot;</td></tr><tr><td>Speed_Mhz</td><td>Bus_Speed_Mhz</td><td>&quot;Bus_Speed_Mhz&quot;</td></tr><tr><td>DMA_Channels</td><td>64</td><td>64</td></tr><tr><td>Width_Bytes</td><td>8</td><td>8</td></tr></table> <h2>If_Else</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>If_Statement</td><td>&quot;A_Destination != Architecture_1&quot;</td><td>&quot;A_Destination != Architecture_1&quot;</td></tr><tr><td>If_Execute</td><td>&quot;1, 2&quot;</td><td>&quot;1, 2&quot;</td></tr><tr><td>Else_Execute</td><td>&quot;3, 4&quot;</td><td>&quot;3, 4&quot;</td></tr><tr><td>Field_Statement_1</td><td>Name_X Assign Name_Y OP Name_Z</td><td>&quot;Name_X Assign Name_Y OP Name_Z&quot;</td></tr><tr><td>Field_Statement_2</td><td>Name_X Assign Name_Y OP Name_Z</td><td>&quot;Name_X Assign Name_Y OP Name_Z&quot;</td></tr><tr><td>Field_Statement_3</td><td>Name_X Assign Name_Y OP Name_Z</td><td>&quot;Name_X Assign Name_Y OP Name_Z&quot;</td></tr><tr><td>Field_Statement_4</td><td>Name_X Assign Name_Y OP Name_Z</td><td>&quot;Name_X Assign Name_Y OP Name_Z&quot;</td></tr><tr><td>Random_Seed</td><td>123457L</td><td>123457L</td></tr><tr><td>_flipPortsHorizontal</td><td>true</td><td>true</td></tr></table> <h2>I_O3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>IO_Name</td><td>&quot;DMA_In&quot;</td><td>&quot;DMA_In&quot;</td></tr><tr><td>IO_Destination</td><td>&quot;Fld_Name_or_String&quot;</td><td>&quot;Fld_Name_or_String&quot;</td></tr><tr><td>IO_Command</td><td>&quot;Fld_Name_or_String&quot;</td><td>&quot;Fld_Name_or_String&quot;</td></tr><tr><td>IO_Instruction</td><td>&quot;Fld_Name_or_String_or_None&quot;</td><td>&quot;Fld_Name_or_String_or_None&quot;</td></tr><tr><td>IO_Bytes</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr><tr><td>IO_Priority</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr><tr><td>IO_Address</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr></table> <h2>Linear_Port5</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;Bus_1&quot;</td><td>&quot;Bus_1&quot;</td></tr><tr><td>Port_Name_1</td><td>&quot;Port_9&quot;</td><td>&quot;Port_9&quot;</td></tr><tr><td>Port_Name_2</td><td>&quot;Port_10&quot;</td><td>&quot;Port_10&quot;</td></tr><tr><td>FIFO_Buffers</td><td>8</td><td>8</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr></table> <h2>Processing</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>/* Template to enter multiple RegEx lines*/\\n input.A_Task_Name = &quot;OSD&quot;\\n input.A_Bytes = Image_Bytes\\n input.A_Task_Flag = true\\n input.Last_Frag = false\\n input.A_Command = &quot;Read&quot;</td><td>/* Template to enter multiple RegEx lines*/\\n input.A_Task_Name = &quot;OSD&quot;\\n input.A_Bytes = Image_Bytes\\n input.A_Task_Flag = true\\n input.Last_Frag = false\\n input.A_Command = &quot;Read&quot;</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>input</td><td>&quot;input&quot;</td></tr></table> <h2>Trans_Src</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Data_Structure_Name</td><td>&quot;Processor_DS&quot;</td><td>&quot;Processor_DS&quot;</td></tr><tr><td>Start_Time</td><td>1.0E-09</td><td>1.0E-9</td></tr><tr><td>Value_1</td><td>1.0/(33.0e6/((Image_Bytes*2)/8))</td><td>6.5454545454545E-4</td></tr><tr><td>Value_2</td><td>2.0</td><td>2.0</td></tr><tr><td>Random_Seed</td><td>123457L</td><td>123457L</td></tr><tr><td>Time_Distribution</td><td>Fixed (Value_1)</td><td>Fixed (Value_1)</td></tr></table> <h2>I_O2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>IO_Name</td><td>&quot;OSD&quot;</td><td>&quot;OSD&quot;</td></tr><tr><td>IO_Destination</td><td>&quot;Display&quot;</td><td>&quot;Display&quot;</td></tr><tr><td>IO_Command</td><td>&quot;Write&quot;</td><td>&quot;Write&quot;</td></tr><tr><td>IO_Instruction</td><td>&quot;Fld_Name_or_String_or_None&quot;</td><td>&quot;Fld_Name_or_String_or_None&quot;</td></tr><tr><td>IO_Bytes</td><td>Image_Bytes/100</td><td>864</td></tr><tr><td>IO_Priority</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr><tr><td>IO_Address</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr></table> <h2>Linear_Port4</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;Bus_1&quot;</td><td>&quot;Bus_1&quot;</td></tr><tr><td>Port_Name_1</td><td>&quot;Port_7&quot;</td><td>&quot;Port_7&quot;</td></tr><tr><td>Port_Name_2</td><td>&quot;Port_8&quot;</td><td>&quot;Port_8&quot;</td></tr><tr><td>FIFO_Buffers</td><td>8</td><td>8</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr></table> <h2>Linear_Port3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;Bus_1&quot;</td><td>&quot;Bus_1&quot;</td></tr><tr><td>Port_Name_1</td><td>&quot;Port_5&quot;</td><td>&quot;Port_5&quot;</td></tr><tr><td>Port_Name_2</td><td>&quot;Port_6&quot;</td><td>&quot;Port_6&quot;</td></tr><tr><td>FIFO_Buffers</td><td>8</td><td>8</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr></table> <h2>SSD</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Sequence_Read_Time</td><td>50.0e-9</td><td>5.0E-8</td></tr><tr><td>Random_Read_Time</td><td>50.0e-6</td><td>5.0E-5</td></tr><tr><td>Write_Access</td><td>50.0e-9</td><td>5.0E-8</td></tr><tr><td>Arch_Setup</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Page_Size</td><td>2048</td><td>2048</td></tr><tr><td>Erase_Access</td><td>50.0e-9</td><td>5.0E-8</td></tr><tr><td>Read_Access_Time</td><td>50.0e-9</td><td>5.0E-8</td></tr><tr><td>Write_Access_Time</td><td>50.0e-9</td><td>5.0E-8</td></tr><tr><td>Erase_Access_Time</td><td>50.0e-9</td><td>5.0E-8</td></tr><tr><td>Flash_Name</td><td>&quot;SSD&quot;</td><td>&quot;SSD&quot;</td></tr><tr><td>Flash_CTRL_Name</td><td>&quot;SSD_Ctrl&quot;</td><td>&quot;SSD_Ctrl&quot;</td></tr></table> <h2>I_O</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>IO_Name</td><td>&quot;Display&quot;</td><td>&quot;Display&quot;</td></tr><tr><td>IO_Destination</td><td>&quot;Fld_Name_or_String&quot;</td><td>&quot;Fld_Name_or_String&quot;</td></tr><tr><td>IO_Command</td><td>&quot;Fld_Name_or_String&quot;</td><td>&quot;Fld_Name_or_String&quot;</td></tr><tr><td>IO_Instruction</td><td>&quot;Fld_Name_or_String_or_None&quot;</td><td>&quot;Fld_Name_or_String_or_None&quot;</td></tr><tr><td>IO_Bytes</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr><tr><td>IO_Priority</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr><tr><td>IO_Address</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr><tr><td>_flipPortsHorizontal</td><td>true</td><td>true</td></tr></table> <h2>Linear_Port2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;Bus_1&quot;</td><td>&quot;Bus_1&quot;</td></tr><tr><td>Port_Name_1</td><td>&quot;Port_3&quot;</td><td>&quot;Port_3&quot;</td></tr><tr><td>Port_Name_2</td><td>&quot;Port_4&quot;</td><td>&quot;Port_4&quot;</td></tr><tr><td>FIFO_Buffers</td><td>8</td><td>8</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr></table> <h2>Linear_Port</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;Bus_1&quot;</td><td>&quot;Bus_1&quot;</td></tr><tr><td>Port_Name_1</td><td>&quot;Port_1&quot;</td><td>&quot;Port_1&quot;</td></tr><tr><td>Port_Name_2</td><td>&quot;Port_2&quot;</td><td>&quot;Port_2&quot;</td></tr><tr><td>FIFO_Buffers</td><td>8</td><td>8</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr></table> <h2>Linear_Bus</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>_explanation</td><td>HardwareDevices-&gt;BusArbiter</td><td>HardwareDevices-&gt;BusArbiter</td></tr><tr><td>Bus_Name</td><td>&quot;Bus_1&quot;</td><td>&quot;Bus_1&quot;</td></tr><tr><td>Bus_Speed_Mhz</td><td>Bus_Speed_Mhz</td><td>533.0</td></tr><tr><td>Burst_Size_Bytes</td><td>100</td><td>100</td></tr><tr><td>Round_Robin_Port_Array</td><td>{&quot;Port_1&quot;, &quot;Port_2&quot;,&quot;Port_3&quot;,&quot;Port_4&quot;,&quot;Port_5&quot;,&quot;Port_6&quot;,&quot;Port_7&quot;,&quot;Port_8&quot;} </td><td>{&quot;Port_1&quot;, &quot;Port_2&quot;, &quot;Port_3&quot;, &quot;Port_4&quot;, &quot;Port_5&quot;, &quot;Port_6&quot;, &quot;Port_7&quot;, &quot;Port_8&quot;}</td></tr><tr><td>Devices_Attached_to_Slave_by_Port</td><td>{{&quot;Device_1&quot;}, {&quot;Device_2&quot;}, {&quot;Device_3&quot;}, {&quot;Device_4&quot;}, {&quot;Device_5&quot;}, {&quot;Device_6&quot;}, {&quot;Device_7&quot;}, {&quot;Device_8&quot;}}</td><td>{{&quot;Device_1&quot;}, {&quot;Device_2&quot;}, {&quot;Device_3&quot;}, {&quot;Device_4&quot;}, {&quot;Device_5&quot;}, {&quot;Device_6&quot;}, {&quot;Device_7&quot;}, {&quot;Device_8&quot;}}</td></tr><tr><td>Width_Bytes</td><td>8</td><td>8</td></tr><tr><td>Arbiter_Mode</td><td>FCFS</td><td>FCFS</td></tr><tr><td>Split_Retry_Flag</td><td>true</td><td>true</td></tr></table> <h2>DRAM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Memory_Name</td><td>&quot;DDR2DRAM_1&quot;</td><td>&quot;DDR2DRAM_1&quot;</td></tr><tr><td>Memory_Speed_Mhz</td><td>RAM_Speed_Mhz</td><td>866.0</td></tr><tr><td>Memory_Size_MBytes</td><td>1000.0</td><td>1000.0</td></tr><tr><td>Access_Time</td><td>RAM_Access_Time</td><td>&quot;Read 1000.0/RAM_Speed_Mhz*2,Prefetch 2.5,Refresh 1000.0/RAM_Speed_Mhz*2,Write 1000.0/RAM_Speed_Mhz*2&quot;</td></tr><tr><td>FIFO_Buffers</td><td>32</td><td>32</td></tr><tr><td>Refresh_Rate_Cycles</td><td>16384</td><td>16384</td></tr><tr><td>Refresh_Cycles</td><td>32</td><td>32</td></tr><tr><td>Memory_Address</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td></tr><tr><td>Controller_Time</td><td>&quot;Cycle_Time * 1.0&quot;</td><td>&quot;Cycle_Time * 1.0&quot;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Width_Bytes</td><td>8</td><td>8</td></tr><tr><td>Memory_Type</td><td>DDR2</td><td>DDR2</td></tr></table> <h2>INT_FLT</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Instruction_Set_Name</td><td>&quot;Atom_InstrSet&quot;</td><td>&quot;Atom_InstrSet&quot;</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;Instruction_Set</td><td>ProcessorGenerator-&gt;Instruction_Set</td></tr><tr><td>Instruction_Set_Text</td><td>/* Instruction Set or File Path. */\\n Mnew Ra Rb Rc Rd Re ; /* Label */\\n ATOM IU BPU VPU ;\\n IU INT_1 ;\\n BPU INT_2 ;\\n VPU FP_1 ;\\n\\nbegin INT_1 ; /* Group */\\n EXTS\t1\t\t ;\\n MOV\t1 2\t\t ;\\n MOVCA 3 7\t\t ;\\n MOVC 3 5\t\t ;\\n OCBI\t1 2\t\t ;\\n OCBP\t1 5\t\t ;\\n SWAP\t1\t\t ;\\n XTRCT 1\t\t ;\\n ADD\t1\t\t ;\\n CMP 1\t\t ;\\n DIV 1\t\t ;\\n DMULS 4\t\t ;\\n DMULU 4\t\t ;\\n DT 1\t\t ;\\n MAC 2 4\t\t ;\\n MUL 4\t\t ;\\n MULU 4\t\t ;\\n MULS 4\t\t ;\\n NEG 1\t\t ;\\n NEGC 1\t\t ;\\n SUB 1\t\t ;\\n SUBC 1\t\t ;\\n SUBV 1\t\t ;\\n AND 1\t\t ;\\n ANDB 4\t\t ;\\n NOT 1\t\t ;\\n OR 1\t\t ;\\n OR_B 4\t\t ;\\n TAS 1\t\t ;\\n TASB 5\t\t ;\\n TST 1\t\t ;\\n TSTB 3\t\t ;\\n XOR 1\t\t ;\\n XORB 4\t\t ;\\n ROTL 1\t\t ;\\n ROTR 1\t\t ;\\n ROTCL 1\t\t ;\\n ROTCR 1\t\t ;\\n SHAD 1\t\t ;\\n SHAL 1\t\t ;\\n SHAR 1\t\t ;\\n SHLD 1\t\t ;\\n SHLL 1\t\t ;\\n SHLR 1\t\t ;\\n SHLL2 1\t\t ;\\n SHLL8 1\t\t ;\\n SHLR8 1\t\t ;\\n SHLL16 1\t\t ;\\n SHLR16 1\t\t ;\\nend INT_1 ;\\n\\nbegin INT_2 ; /* Group */\\n *BF 1 2 ;\\n *BFS 1 2 ;\\n *BT 1 2 ;\\n *BTS 1 2 ;\\n *BRA 1 2 ;\\n *BRAF 3 ;\\n *BSR 2 ;\\n *BSRF 3 ;\\n *JMP 3 ;\\n *JSR 3 ;\\n *RTS 3 ;\\n l_s 1 ;\\nend INT_2 ;\\n\\nbegin FP_1 ; /* Group */\\n FADD 3 4 ;\\n FCMP 2 4 ;\\n FDIV 12 13 ;\\n FLOAT 3 4 ;\\n FMAC 3 4 ;\\n FMUL 3 4 ;\\n FSQRT 11 12 ;\\n FSUB 3 4 ;\\n FTRC 3 4 ;\\n DFADD 7 9 ;\\n DFCMP 3 5 ;\\n DFCNVDS 4 5 ;\\n DFCNVSD 3 5 ;\\n DFDIV 24 26 ;\\n DFLOAT 3 5 ;\\n DFMUL 7 9 ;\\n DFSQRT 23 25 ;\\n DFSUB 7 9 ;\\n DFTRC 4 5 ;\\n FTRV 7 ;\\n GFMOV 1 2 ;\\n GFIPR 4 5 ;\\n GFRCHG 1 4 ;\\n GFTRV 5 8 ;\\nend FP_1 ;</td><td>/* Instruction Set or File Path. */\\n Mnew Ra Rb Rc Rd Re ; /* Label */\\n ATOM IU BPU VPU ;\\n IU INT_1 ;\\n BPU INT_2 ;\\n VPU FP_1 ;\\n\\nbegin INT_1 ; /* Group */\\n EXTS\t1\t\t ;\\n MOV\t1 2\t\t ;\\n MOVCA 3 7\t\t ;\\n MOVC 3 5\t\t ;\\n OCBI\t1 2\t\t ;\\n OCBP\t1 5\t\t ;\\n SWAP\t1\t\t ;\\n XTRCT 1\t\t ;\\n ADD\t1\t\t ;\\n CMP 1\t\t ;\\n DIV 1\t\t ;\\n DMULS 4\t\t ;\\n DMULU 4\t\t ;\\n DT 1\t\t ;\\n MAC 2 4\t\t ;\\n MUL 4\t\t ;\\n MULU 4\t\t ;\\n MULS 4\t\t ;\\n NEG 1\t\t ;\\n NEGC 1\t\t ;\\n SUB 1\t\t ;\\n SUBC 1\t\t ;\\n SUBV 1\t\t ;\\n AND 1\t\t ;\\n ANDB 4\t\t ;\\n NOT 1\t\t ;\\n OR 1\t\t ;\\n OR_B 4\t\t ;\\n TAS 1\t\t ;\\n TASB 5\t\t ;\\n TST 1\t\t ;\\n TSTB 3\t\t ;\\n XOR 1\t\t ;\\n XORB 4\t\t ;\\n ROTL 1\t\t ;\\n ROTR 1\t\t ;\\n ROTCL 1\t\t ;\\n ROTCR 1\t\t ;\\n SHAD 1\t\t ;\\n SHAL 1\t\t ;\\n SHAR 1\t\t ;\\n SHLD 1\t\t ;\\n SHLL 1\t\t ;\\n SHLR 1\t\t ;\\n SHLL2 1\t\t ;\\n SHLL8 1\t\t ;\\n SHLR8 1\t\t ;\\n SHLL16 1\t\t ;\\n SHLR16 1\t\t ;\\nend INT_1 ;\\n\\nbegin INT_2 ; /* Group */\\n *BF 1 2 ;\\n *BFS 1 2 ;\\n *BT 1 2 ;\\n *BTS 1 2 ;\\n *BRA 1 2 ;\\n *BRAF 3 ;\\n *BSR 2 ;\\n *BSRF 3 ;\\n *JMP 3 ;\\n *JSR 3 ;\\n *RTS 3 ;\\n l_s 1 ;\\nend INT_2 ;\\n\\nbegin FP_1 ; /* Group */\\n FADD 3 4 ;\\n FCMP 2 4 ;\\n FDIV 12 13 ;\\n FLOAT 3 4 ;\\n FMAC 3 4 ;\\n FMUL 3 4 ;\\n FSQRT 11 12 ;\\n FSUB 3 4 ;\\n FTRC 3 4 ;\\n DFADD 7 9 ;\\n DFCMP 3 5 ;\\n DFCNVDS 4 5 ;\\n DFCNVSD 3 5 ;\\n DFDIV 24 26 ;\\n DFLOAT 3 5 ;\\n DFMUL 7 9 ;\\n DFSQRT 23 25 ;\\n DFSUB 7 9 ;\\n DFTRC 4 5 ;\\n FTRV 7 ;\\n GFMOV 1 2 ;\\n GFIPR 4 5 ;\\n GFRCHG 1 4 ;\\n GFTRV 5 8 ;\\nend FP_1 ;</td></tr><tr><td>Record_Set_Name</td><td>&quot;Record_Set_Name&quot;</td><td>&quot;Record_Set_Name&quot;</td></tr></table> <h2>Processor</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>For Cache\\nI-Cache: 2-Way associate reduces the size by half. Instr is 16 bits. \\nLine size is 32 Bytes and so Words per line is 16\\nI-Cache: 2-Way associate reduces the size by half. Data is 32 bits. \\nLine size is 32 Bytes and so Words per line is 8. If split into RAM + \\ncache, then make this half and include an external block for the RAM.\\nThe Miss for the D_1 will point to this. The I-1 miss will point \\nto the regular cache.</td><td>For Cache\\nI-Cache: 2-Way associate reduces the size by half. Instr is 16 bits. \\nLine size is 32 Bytes and so Words per line is 16\\nI-Cache: 2-Way associate reduces the size by half. Data is 32 bits. \\nLine size is 32 Bytes and so Words per line is 8. If split into RAM + \\ncache, then make this half and include an external block for the RAM.\\nThe Miss for the D_1 will point to this. The I-1 miss will point \\nto the regular cache.</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Processor_Name</td><td>&quot;ATOM&quot;</td><td>&quot;ATOM&quot;</td></tr><tr><td>Processor_Setup</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value ; \\nProcessor_Instruction_Set: Atom_InstrSet ; \\nNumber_of_Registers: 16 ; \\nProcessor_Speed_Mhz: 1330.0 ; \\nContext_Switch_Cycles: 100 ; \\nInstruction_Queue_Length: 60 ; \\nNumber_of_Pipeline_Stages: 13 ; \\nNumber_of_INT_Execution_Units: 2 ; \\nNumber_of_FP_Execution_Units: 1 ; \\nNumber_of_Cache_Execution_Units: 3 ; \\nI_1: {Cache_Speed_Mhz=1330.0, Size_KBytes=32.0, Words_per_Cache_Line=16, Cache_Miss_Name=L2} \\nD_1: {Cache_Speed_Mhz=1330.0, Size_KBytes=32.0, Words_per_Cache_Line=8, Cache_Miss_Name=L2} \\nL2: {Cache_Speed_Mhz=1330.0, Size_KBytes=32.0, Words_per_Cache_Line=8, Cache_Miss_Name=DDR2DRAM_1} </td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value ; \\nProcessor_Instruction_Set: Atom_InstrSet ; \\nNumber_of_Registers: 16 ; \\nProcessor_Speed_Mhz: 1330.0 ; \\nContext_Switch_Cycles: 100 ; \\nInstruction_Queue_Length: 60 ; \\nNumber_of_Pipeline_Stages: 13 ; \\nNumber_of_INT_Execution_Units: 2 ; \\nNumber_of_FP_Execution_Units: 1 ; \\nNumber_of_Cache_Execution_Units: 3 ; \\nI_1: {Cache_Speed_Mhz=1330.0, Size_KBytes=32.0, Words_per_Cache_Line=16, Cache_Miss_Name=L2} \\nD_1: {Cache_Speed_Mhz=1330.0, Size_KBytes=32.0, Words_per_Cache_Line=8, Cache_Miss_Name=L2} \\nL2: {Cache_Speed_Mhz=1330.0, Size_KBytes=32.0, Words_per_Cache_Line=8, Cache_Miss_Name=DDR2DRAM_1} </td></tr><tr><td>Pipeline_Stages</td><td>\\nStage_Name Execution_Location Action Condition ; \\n1_FETCH1 I_1 instr none ; /* Fetch */\\n2_FETCH2 I_1 wait none ; /* Fetch */\\n3_DATA0 D_1 read none ; /* Data */\\n4_DATA1 D_1 wait none ; /* Data */\\n5_DATA2 none exec none ; /* Data Pipeline */\\n6_DATA3 none exec none ; /* Data Pipeline */\\n7_DATA4 none exec none ; /* Data Pipeline */\\n8_EXEC0 ATOM exec none ; /* Execute Instruction */ \\n9_EXEC1 none exec none ; /* Processing */\\n10_EXEC2 none exec none ; /* Processing */\\n11_EXEC3 none exec none ; /* Processing */\\n12_EXEC4 ATOM Wait none ; /* Wait Execute */\\n13_EXEC5 D_1 write none ; /* Store */</td><td>\\nStage_Name Execution_Location Action Condition ; \\n1_FETCH1 I_1 instr none ; /* Fetch */\\n2_FETCH2 I_1 wait none ; /* Fetch */\\n3_DATA0 D_1 read none ; /* Data */\\n4_DATA1 D_1 wait none ; /* Data */\\n5_DATA2 none exec none ; /* Data Pipeline */\\n6_DATA3 none exec none ; /* Data Pipeline */\\n7_DATA4 none exec none ; /* Data Pipeline */\\n8_EXEC0 ATOM exec none ; /* Execute Instruction */ \\n9_EXEC1 none exec none ; /* Processing */\\n10_EXEC2 none exec none ; /* Processing */\\n11_EXEC3 none exec none ; /* Processing */\\n12_EXEC4 ATOM Wait none ; /* Wait Execute */\\n13_EXEC5 D_1 write none ; /* Store */</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Processor_Bits</td><td>32</td><td>32</td></tr></table> <h2>Latency_Out</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>_flipPortsHorizontal</td><td>true</td><td>true</td></tr></table> <h2>RTOS</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>Latency</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Frame_Time</td><td>1.0 / FPS /* DO NOT MODIFY */</td><td>0.005</td></tr></table> <h2>Histogram</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>FPS</td><td>FPS</td><td>200</td></tr><tr><td>Frame_Time</td><td>1.0 / FPS /* DO NOT MODIFY */</td><td>0.005</td></tr><tr><td>Image_Bytes</td><td>Image_Bytes</td><td>86400</td></tr><tr><td>_flipPortsHorizontal</td><td>true</td><td>true</td></tr><tr><td>Cycle_Time</td><td>1.0E-06/VPSS_Speed_Mhz</td><td>2.4691358024691E-9</td></tr><tr><td>Width_Bytes</td><td>8</td><td>8</td></tr></table> <h2>Resizer</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Device_Name</td><td>&quot;Resizer&quot;</td><td>&quot;Resizer&quot;</td></tr><tr><td>Cycle_Time</td><td>1.0E-06/VPSS_Speed_Mhz</td><td>2.4691358024691E-9</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>DRAM_Name</td><td>&quot;DDR3DRAM_2&quot;</td><td>&quot;DDR3DRAM_2&quot;</td></tr></table> <h2>H3A</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Device_Name</td><td>&quot;H3A&quot;</td><td>&quot;H3A&quot;</td></tr><tr><td>Cycle_Time</td><td>1.0E-06/VPSS_Speed_Mhz</td><td>2.4691358024691E-9</td></tr><tr><td>Width_Bytes</td><td>8</td><td>8</td></tr><tr><td>DRAM_Name</td><td>&quot;DDR3DRAM_1&quot;</td><td>&quot;DDR3DRAM_1&quot;</td></tr></table> <h2>Previewer</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Device_Name</td><td>&quot;Previewer&quot;</td><td>&quot;Previewer&quot;</td></tr><tr><td>Cycle_Time</td><td>1.0E-06/VPSS_Speed_Mhz</td><td>2.4691358024691E-9</td></tr><tr><td>DRAM_Name</td><td>&quot;DDR3DRAM_2&quot;</td><td>&quot;DDR3DRAM_2&quot;</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr></table> <h2>Switch</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>Image_Sensor</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>FPS</td><td>500.0e6/(Image_Bytes/8)</td><td>46296.2962962963</td></tr><tr><td>Frame_Time</td><td>1.0 / FPS /* DO NOT MODIFY */</td><td>2.16E-5</td></tr><tr><td>Image_Bytes</td><td>Image_Bytes</td><td>86400</td></tr></table> <h2>Buffer</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>DDR_Freq</td><td>RAM_Speed_Mhz</td><td>866.0</td></tr><tr><td>Bus_Speed</td><td>Bus_Speed_Mhz</td><td>533.0</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>1.5E-4</td></tr></table> <h2>CCDC</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Device_Name</td><td>&quot;CCDC&quot;</td><td>&quot;CCDC&quot;</td></tr><tr><td>Cycle_Time</td><td>1.0E-06/VPSS_Speed_Mhz</td><td>2.4691358024691E-9</td></tr><tr><td>Width_Bytes</td><td>8</td><td>8</td></tr><tr><td>DRAM_Name</td><td>&quot;DDR3DRAM_1&quot;</td><td>&quot;DDR3DRAM_1&quot;</td></tr></table> <h2>Database</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>*.xml, *.csv files abs or rel (./) path\\n -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n -- match_all.field not allowed</td><td>*.xml, *.csv files abs or rel (./) path\\n -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n -- match_all.field not allowed</td></tr><tr><td>Linking_Name</td><td>&quot;DMADatabase&quot;</td><td>&quot;DMADatabase&quot;</td></tr><tr><td>fileOrURL</td><td>&nbsp;</td><td>&quot;&quot;</td></tr><tr><td>Data_Structure_Text</td><td>A_Task_Name\tA_Instruction\tA_IDX\tA_Task_Source\tBurst_Word_Size\tA_Task_Address A_Command\tA_Bytes\t\tA_Priority\tA_Destination \\nOSD\t Load\t 0\tDDR2DRAM_1\t 64\t 1 Read\t\t(Image_Bytes) 1\t DMA ;\\nHistogram\tLoad\t 0\tSSD\t\t 64\t 2 Read\t\t(Image_Bytes) 1\t DMA ;</td><td>A_Task_Name\tA_Instruction\tA_IDX\tA_Task_Source\tBurst_Word_Size\tA_Task_Address A_Command\tA_Bytes\t\tA_Priority\tA_Destination \\nOSD\t Load\t 0\tDDR2DRAM_1\t 64\t 1 Read\t\t(Image_Bytes) 1\t DMA ;\\nHistogram\tLoad\t 0\tSSD\t\t 64\t 2 Read\t\t(Image_Bytes) 1\t DMA ;</td></tr><tr><td>Input_Fields</td><td>&quot;ID&quot;</td><td>&quot;ID&quot;</td></tr><tr><td>Lookup_Fields</td><td>&quot;ID&quot;</td><td>&quot;ID&quot;</td></tr><tr><td>Output_Expression</td><td>&quot;output = match&quot; /* FORMAT output = match.fieldb */</td><td>&quot;output = match&quot;</td></tr><tr><td>Mode</td><td>Read</td><td>Read</td></tr></table> <h2>Architecture_Setup</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Field_Name_Mapping</td><td>/* First row contains Column Names. */\\nExternal_Field_Name Internal_Field_Name ; \\nA_Address A_Address ; \\nA_Bytes A_Bytes ; \\nA_Data A_Data ; \\nA_IDX A_IDX ; \\nA_Instruction A_Instruction ; \\nA_Priority A_Priority ; \\nA_Source A_Source ; \\nA_Destination A_Destination ; \\nA_Task_ID A_Task_ID ; \\nA_Time A_Time ; \\n</td><td>/* First row contains Column Names. */\\nExternal_Field_Name Internal_Field_Name ; \\nA_Address A_Address ; \\nA_Bytes A_Bytes ; \\nA_Data A_Data ; \\nA_IDX A_IDX ; \\nA_Instruction A_Instruction ; \\nA_Priority A_Priority ; \\nA_Source A_Source ; \\nA_Destination A_Destination ; \\nA_Task_ID A_Task_ID ; \\nA_Time A_Time ; \\n</td></tr><tr><td>Routing_Table</td><td>/* First row contains Column Names. \\nSource_Node Destination_Node Hop Source_Port ; */\\n</td><td>/* First row contains Column Names. \\nSource_Node Destination_Node Hop Source_Port ; */\\n</td></tr><tr><td>Number_of_Samples</td><td>1</td><td>1</td></tr><tr><td>Statistics_to_Plot</td><td>&quot;ATOM_PROC_Utilization_Min, ATOM_PROC_Utilization_Mean, ATOM_PROC_Utilization_Max&quot;</td><td>&quot;ATOM_PROC_Utilization_Min, ATOM_PROC_Utilization_Mean, ATOM_PROC_Utilization_Max&quot;</td></tr><tr><td>Internal_Plot_Trace_Offset</td><td>2</td><td>2</td></tr><tr><td>Listen_to_Architecture_Options</td><td>Pipeline</td><td>Pipeline</td></tr></table> <h2>Display</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Title</td><td>&quot;Detailed Processor Activity&quot;</td><td>&quot;Detailed Processor Activity&quot;</td></tr><tr><td>Lines_Buffered</td><td>1</td><td>1</td></tr><tr><td>Rows_Displayed</td><td>20</td><td>20</td></tr><tr><td>Columns_Displayed</td><td>75</td><td>75</td></tr><tr><td>Font_Type</td><td>Lucida Console</td><td>Lucida Console</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr></table>

Implements the application of Intel ATOm processor in a Camera application