Industrial and Computing Systems

Programmable Automation Controller
Designing a full redundant large factory system
Data Acquisition System
Simple data acquisition system to select between DMA vs processor driven
Display Systems
Selecting the components for a multi-display system with sensor, video encoding and front-end display processing
Printing Systems
Modeling a Fax or Printer system
Large-Scale Servers
12 Processor modules with 8 cores each conencted to a PCIe to 4 DRAM devices using a feature called Dynamic Instantiation
High Performance Computer
Creating an OpenVPX backplane for an outer space application
Distributed Memory Architecture
12 Processor modules with 8 cores each conencted to a PCIe to 4 DRAM devices using a feature called Dynamic Instantiation

SNS RF Hardware Control System

The modeling and simulation described below was performed for the SNS project under the guidance of Lawrence Berkeley Labs.
Mirabilis design has modeled, simulated and analyzed the RF Hardware Control Block using VisualSim. The starting assumptions, simulation models and the live simulations are all included in this document. Please feel free to modify the simulation parameters and redraw the simulation results.

Conclusion

The Control system is more latency dependent than resource limited. There is occasional queue overflows with queues set to length of 100. There were scenarios when the latency exceeded the maximum limit of 120 ns. The system is not resource limited as presently configured, as several system elements must be accessed sequentially, which does impact overall latency of incoming samples. This seems to be the direction of the investigation. The timing plots in the model could be used to study the latency issue with just a few samples to see the relationships more closely.
The intent of this experiment was to build a quick model and show the type of results the Control System Model would generate. A more detailed analysis of the internal timing, and gaining a better picture of the FPGA portion, which may be critical to addressing the latency issue

Model Assumptions

The Sensor Model has the following parameters:

Bus Speed 66.0 Mhz
SDRAM Speed 50.0 Mhz
CPU Speed 200.0 Mhz
Cache Speed 200.0 Mhz
Sensor Speed N.N Mhz
Sensor Size M Bytes

The provided states that the input rate of 40.0 MS/sec @ 16 bits of analog sample. Internally, the Sensor Model uses 32 bits for each Word, so translated 40.0 MS/sec @ 16 bits to 20.0 MS/sec @ 32 bits. This parameter setting overflowed the internal queues.

Sensor Model Description

The Sensor Model demonstration model accepts an incoming stream of data and directs a propotion to a DMA channel mechanism that the user can
select. The maximum number of DMA channels is three. The input rate is using a fixed distribution, however, the user could use an exponential interarrival, normal, or uniform random distribution. The processing rates (Mhz) for the internal elements are user settable. The model can also set background processing to the CPU element, similar to an OS, or RTOS loading. The model also contains a detailed Cache model, which shows statistically generated addresses.

Figure 1: Visualsim Simulation Model of the Control System

The Sensor Model generates a time line of CPU, SDRAM, Cache, Bus, and DMA activity. It also generates utilization rates for the CPU, SDRAM, Cache, and Bus. The last figure shows Cache Activity, where cache misses occur when the 'Cur' pointer exceeds the 'Max' pointer, or is less than the Min Cache Address Pointer.

The Sensor Model below is a live simulation. Click on any block and modify the provided parameters. The model will be simulated and the results will be redrawn.

Figure 2: Interactive Simulation of the Control System. Change the parameter values and click on GO. The simulation will be executed and the plots will be updated.

Notes:

The model was built in a few hours and analyzed over a couple of days.
The model was built based on the provided block diagram and the datasheet information.