Architecture exploration, performance and power analysis early in the design flow are mandatory in modern SoC design flow due to complex multi-threaded applications and multi-core processing requirements. Instruction Set Simulator or ISS of a selected processor plays a very important role. However, Current Instruction Set Simulators (ISS) and platform modelers have detailed functional execution, tuned to verify an existing or selected platform. These require software to be available, detailed peripheral description and long simulation times. This also requires significant amount of time for integrating memory subsystem, interconnects, processor models and running application software itself.
We at Mirabilis Design arrived with statistical processor models that are customized using parameters from the vendor datasheet to describe a processor family with 80% accuracy. The parameters include internal device characteristics, pipeline stage descriptions and the instruction set. The resulting processor model has detailed pipeline activity interaction, interaction of instruction + data cache (Harvard Architecture) and internal instruction stream processing.
Accurate analysis of throughput, utilization, thread activity, stalls, hit-miss ration, pre-fetch, context cycles and state change has been generated and correlated with hardware. The processor model can generate power statistics using dynamic state change and management algorithms. Combining multiple processor instances and connecting to other configurable peripherals create a platform model. This technology is being incorporated in the VisualSim Processor Modeling Toolkit from Mirabilis Design. Future work involves extensions for better pipeline to pipeline interaction across cores, memory-specific instruction and hardware threads.