Have you ever thought of having a systematic approach for selecting right processor for your upcoming SoC? Absolutely, every day we all think about it and finally go with our “gut feeling”. Selection of processor is becoming extremely complex day by day and is not at a straightforward task as opposed to early days of SoC development.
Now we have many complex requirements including low power consumption, parallel processing, low latency and high bandwidth. We tend to go with our previous experience as we will have very little amount information about the design. If we consider having a multi-core processor; then the parallel programming paradigms become increasingly attractive to leverage all available resources.
Although processors logically access the same memory, on-chip cache hierarchies are crucial to achieving fast performance for the majority of memory references made by processors. In one of our multi-media SoC project, based on analytical methods we decided architecture with a dual core processor with shared memory architecture. But once we progress through the design cycle we noticed that the performance figures were nearly 50% lesser and noticed that the memory read latency was high. This forced us to change the memory hierarchy and also include a FPGA for running performance intensive tasks.
At the same time we also noticed that power consumption of FPGA itself was consuming nearly 30% of total system power consumption. Modeling using C/C++/SystemC is costly in terms of modeling time and also lack of framework to model custom resources. Modeling and simulation of complete SoC platform with VisualSim provided us guidelines to select the right processor, memory subsystem and also indentify possible bottlenecks.
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