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Templates The Pre-Built models provide a convenient mechanism to learn quickly all the features of VisualSim. Every operation of each block is explained using examples. There are examples that can be used as a starting point for many design exploration studies. All examples are documented. |
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Table of Content
Demonstration Models and Example SystemsMethodologySystem Hardware Distribution
Traffic Generator, Cycle-accurate cache, AHB Bus and Statistical
Memory
Software
Trace Traffic Generator, Cycle-accurate cache, AHB Bus and Statistical Memory Trace Traffic Generator, Cycle-accurate cache, AHB Bus and cycle-accurate Memory Distribution Traffic, Cycle-accurate Cache, AXI Crossbar and Cycle-accurate Memory Trace Traffic Generator, Cycle-accurate Cache, AXI Crossbar and Cycle-accurate Memory SoC Power Modeling Evaluating Power Gating (set Partitioning to "HW" and set power_gating to true) Comparision Model SDRAM vs Flash Comparision Model SDRAM vs Hard Drive Load Balancing DDR3 Model Mapping
software tasks to hardware architecture
Partitioning application into hardware and software Consolidated trace with full system model of Android-based SmartPhone Address-based software design and optimization Software Power Modeling  AutomotiveMulti-Protocol- CAN, Ethernet, EtherSwitch and Gateway SH4 Model ABS Demo Model DescriptionCAN Demo Model Power FlexRayIndustrialData Acquisition Demo Model DescriptionFax Machine Demo ModelProcessorFreescale PowerPC 7410 running Synthetic Aperture Radar software Demo ModelPowerPC 7410 with the Altivec Processing Engine. This model includes the off-chip cache and DRAM. ARM7 TDMI Demo Model Models a dual processor system using a dual-ported cache and memory, and a AHB bus. This model runs a AES Encryption algorithm. The code is located in $VS/HAL/ARM7_ARM8_Platform_Models/aes/aes.c file. ARM8-Cortex Demo Model Models a single processor system using a cache, memory, and a AHB bus. This model runs the same AES Encryption algorithm as the ARM7-TDMI model. Compare the results of this simulation against the ARM7 model. Xilinx-MicroBlaze Demo Model Models the MicroBlaze and runs a example code. The interesting part of this model is that it handles an interrupt available in the MicroBlaze instruction set. When this instruction is seen in the pipeline, it makes a request to the external Scheduler. Renesas SH4 Family Demo Model Description ARM9 Processor Demo Model Description Xilinx PowerPC 405 Demo Model TIC64 DSP Demo Model Nehalem Processor
Xeon Demo Model2 ARM Cortex A9 Dual Core Demo Model Intel ATOM Processor Demo Model Marvel PXA320 Processor Demo Model Coldfire Processor Demo Model Spark Dhrystone Demo Model PowerPC 7447A Demo Model PowerPC 8641D Demo Model Network Processor Demo Model1 8-core IBM Cell Processor Model Demo Model Multi-Processor HPC with SerialRapidIO as Interconnect Demo Model Multi-Processor System with PCIe as Interconnect Demo Model1 Demo Model2 StandardsSoC-levelAMBA-AXIAMBA-AHB/APB
Network-on-ChipAMBA-AHB + AXICore Connect
Board-LevelPCI/PCI-XSPI 3.0Network-Level
Rapid IO
Network3G Demo ModelXon-Xoff Demo ModelGiE Demo ModelSwitched Ethernet Demo Model DescriptionRPR Demo Model DescriptionRP3SPI3 Demo Model DescriptionNetworkingTCP Header Compression Demo Model DescriptionOVS Demo ModelDeficit_RR Demo ModelVirtual Channel Demo ModelAudio-Video BridgingMulti-Node AVB System- Demo ModelMulti-Node AVB System with Bridge- Demo ModelLarge AVB Network using Dynamic Instantiation- Demo Model |
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Non-Functional AnalysisNon Functional Analysis with Redundant processing resource Demo Model |