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Blog Posts
- Visit Mirabilis Design at Chiplet Summit 2026 — Booth 314
- Mirabilis Design – 2025 Annual Newsletter
- VisualSim 2610 System-Level Modeling: New Python, RF, Power, and Multi-Domain Simulation Capabilities
- Build System Models in Days, Not Months
- Architecting for Efficiency: Measuring and Managing Power from Chiplet to System
- Webinar: Master SoC Architecture Trade-Offs
- July 2025: Driving Innovation: VisualSim Hits the Road, the Classroom, and Industry
- Optimizing Automotive Electronics Architecture for Autonomous and Electric Vehicles Using System-Level Modeling
- RISC-V architecture exploration using VisualSim Architect.
- Architecture Exploration of ARM-based SoC and Chiplets
- ARM-Based SoC Design: Mastering System-Level Modeling
- New System-Level IP Library for Cadence Tensilica Processors
- Arteris FlexNoC and Ncore Network-on-Chip IPs
- What is Architectural Queueing?
- Webinar on Multi-Core Scheduling – Register Today!
- System-Level Scheduling for Multi-Core Architectures
- What is Architecture?
- Webinar- 23 January, 2025
- A Comprehensive Approach to Power & Performance Optimization
- Standards-Based Chiplets vs. Proprietary Designs
- Chiplet: Redefining Modular Semiconductor Architectures
- Why Chiplets Have Become Essential in a Post-Moore’s Law World
- Webinar- 14th November 2024
- Mirabilis Design at ELIV
- ARM corelink, Arteris NoC, UCIe, Bunch-of-wires, CXL and PCIe
- Webinar: ARM corelink, Arteris NoC, UCIe, Bunch-of-wires, CXL and PCIe
- Digital Avionics Systems Conference (DASC)- Mirabilis Design
- Early analysis of UAV using Modeling and Simulation
- Digital Twin | AI-drives Visual Picture of the Power Flow
- ARM vs RISC-V Cores | System level Comparison-Latency, Power
- Hardware Software Partitioning- Simulations and Discussions
- Functional Safety for Braking System through ISO 26262
- Reducing Power Consumption | Early System-Level Modeling
- Switch Design for Optimal Service Quality
- Design UCIe-based Multi-die SoC with VisualSim
- Optimizing Aircraft Avionics for Next-Gen Requirements
- Architecture Exploration- Managing Product Lifecycle
- Accelerating Architecture Exploration for FPGA Selection
- Optimizing Consumer Electronics Architectures
- VisualSim Architect TTEthernet
- Virtual Experiments with Zynq 7000
- Power Management with Modeling and Simulation
- DAC 2024 with Mirabilis Design
- VisualSim – Power Solution
- Crack the Power Code
- Selecting the Right System Modeling Software
- All about Blockchain
- How is a Microprocessor different from Integrated Circuit?
- Impact of AI in Architecture Exploration & System Simulation
- Unleashing the Potential of AI in Simulation
- System level SOC Power Modeling
- Achieving 95%+ Accurate Power Measurement
- (FPGA) Field Programmable Gate Array Application
- Field-Programmable Gate Arrays (FPGAs)
- VisualSim AMD-Xilinx Versal FPGA
- System level SoC Power Modeling
- Adaptive Voltage & Frequency Scaling
- Do you really need AI predictions for everything?
- Mapping signal processing algorithms on AMD-Xilinx Versal to meet timing & power constraints
- Power Optimization for Electric Vehicle
- Exploring Enhancements for Electric Vehicle Range
- Webinar: Processing – Turning IoT Data into Intelligence
- Webinar: Modeling abstractions, Accuracy and Applications. April 05, 2023
- Webinar: Mapping SysML behavior model to the VisualSim Architecture Model
- Cyber-Physical System Design from Mirabilis Design
- What type of a simulator does VisualSim contain?
- What is the accuracy of VisualSim models?
- Can VisualSim be used to model to avionics?
- Can VisualSim be used to model to avionics?
- How do you measure the AXI bus throughput using VisualSim?
- How does VisualSim measure Power?
- What is architecture exploration of electronics?
- Hardware-Software Partitioning vs Processor Performance Tuning
- Selecting the Right Processor for your Application
- Avionics Failures can be avoided
- Architecture Challenges in Avionics Systems
- Designing Avionics Systems for Performance, Power and Optimize for Failure Analysis
- Effective and Lower-Cost Alternates to Virtual Prototypes and Instruction Set Simulators
- Future of Electronic Design Continues to be Excel
- Running Benchmarks on high-performance Hybrid Processor Models
- Designing Processor pipeline with Cycle-Accurate Functional Architecture Model.
- Not PowerPoint; Not Word; Digital Twin is the best for Communication
- Integrating SysML use cases into the product implementation
- TSN Network Scaling Presentation at the Automotive Ethernet Conference 2023
- Optimizing Aircraft Avionics for Next-Gen requirements using Digital Twin and MBSE
- What is a Full System Dynamic Simulation?
- Selecting the right hardware configuration for the signal processing platform
- System Simulation of Wired and Wireless Designs
- Managing Product Lifecycle Through Architecture Exploration
- Rethinking the System Design Process
- February 2022 Newsletter
- Power Modeling and Estimation in Early System Design, Part 1
- System-level optimization challenges and architecture exploration benefits
- Application of the Hybrid Processor – VisualSim AI Processor Designer
- The Hybrid Processor Model
- VisualSim AI Processor Designer – Create the Most Effective Processor Designs
- Artificial Intelligence to Address Real Challenges in System Design
- January 2022 Newsletter
- New Intel Chipsets
- New Intel 20 core, 40 thread Sapphire Rapids XEON Processor
- Interrupts
- Intel/SiFive RISC-V Processor Design
- Quantum computer material software
- A store queue and the maths behind it.
- AMD’s 3D-V-Cache memory
- National Institute of Standards and Technology (NIST) atomic mixer
- AFRL, AI or Neural/Synapse Processing
- INTEL, 2nm Chip Neural Processing
- Nvidia, Deep Learning, as used with GPU-Accelerated Servers
- INTEL’s latest H20 Optane memory
- IBM New Memory Class, potential for Neural Processing
- How feasible are 2D film transistors and what lies in the future?
- Ford’s GPS-based headlights
- Light detect and Ranging (LiDAR)
- Queueing Theory, Little’s Law
- Spectre security attack, Intel and AMD
- Digital System Power, Wireless Power Transmission
- System Level Modeling and Analysis of Processors and SoC Designs
- How L1 and L2 memory chips fit into modern processor chips
- Fine-Grained Performance and Power Analysis in 10 Hours using a Statistical Instruction Set Processor Simulator
- Investment in Avionics spurs new systems engineering methodologies
- Volkswagen plans to design own autonomous-driving processor chips
- Why do we need system modeling?
- Stochastic Modeling; over, under Delay importance
- Processing Basics
- Apple M2 Chip using AI or deep learning
- Google Quantum Sycamore processor
- Earthquake Prediction using AI or deep learning
- Quantum counting algorithm
- Quantum Computer Service feasibility over the Internet
- Quantum Internet
- Intel FPGA, Neural Processor (AI)
- Significance of early system analysis of AVB based Systems
- Apple Neural Processor
- How full-scale modeling and simulation achieved Quality-of-Service?
- How can simulation aid in designing of Data-Centers?
- What is a Data Center?
- Graph Theory definitions:
- Digital System Power, Dual Voltage Processor
- Control Flow, or Task Graph traversal; concurrent programming:
- Directed Graph (no loops) vs. Acyclic Directed Graph (w/loops)
- Digital System Power, Processor Performance analysis and benchmarking
- Simple Directed Graph Example:
- Directed Acyclic Graph or Task Graph Reduction, Simplification
- Digital System Power & Processor Power Considerations
- Directed Acyclic Graph or Task Graph
- Digital System Power, Processor Power Considerations
- Digital System Power, Thermal Design Power
- Digital System Power Management ICs
- Digital System EV Battery-Type Considerations: Cycles
- Digital System Power for GPUs
- Digital System Power for Robotics
- Digital System EV Battery Considerations
- Digital System Power for Sensors and Analog Components
- Digital System On-Chip Electro-Migration relation to Power
- Digital System Hardware Power Monitor
- Digital System Strategies to Reduce Power
- Digital System Power Table Configuration
- Digital System Device Junction Temperature vs. Power
- Digital System Vapor Chamber vs. Heat Sink
- Digital System Centralized vs. Distributed Power Management
- How to order Digital System Task or Thread Power?
- VisualSim vs. Simulink, how to choose your ideal simulation platform?
- How to interpret Digital System Peak vs. Average Power?
- Accurate Measurement of Latency and Throughput of Time Sensitive Networks
- Exploring the performance and power management of a real-time video application
- Power Management of Hybrid and Electric Vehicles
- Performance and Power Analysis of Internet of Things devices
- AUTONOMOUS DRIVER ASSISTANCE SYSTEMS (ADAS)
- Architecture Exploration of System-on-Chip
- Architecture Exploration of Artificial Intelligence/Machine Learning Applications and Processors
- Webinar: Capacity Planning and Power Management of Data Centers | Date: April 6, 2021
- Early Exploration of AI Algorithms and Processors
- Benefits of AMBA AXI over AMBA AHB for display systems
- Accelerating Architecture Exploration for FPGA Selection and System Design
- Dual Channel DDR
- Architecting AdvancedTCA design using rapid Visual Prototyping
- Hardware-Software Partitioning in System-on-Chip (SoC)
- RapidIO-Interconnecting PPC with clock and I/O
- AMBA-AHB Multilayer Bus matrix with self-Motivated Arbitration scheme.
- The ARM AMBA: Corelink CMN-600 the Coherent Mesh Network ; providing high data transfer rates.
- Improving the throughput of the products involving processors.
- An overview of the VisualSim architect features
- Realizing customer requisite for efficient solution
- Ways to confirm Integrated Modular Avionics (IMA) Architecture Decisions
- Ways to improve the system level model implementation
- From marketing requirements to product development – a systematic approach
- Improving Power Management to gain product success
- Do multiple processor cores yield higher performance?
- Eliminate Distributed System Design Risks
- Right Design Decisions with Early System Exploration
- Importance of Performance modeling and trade-off analysis
- System Design with Early System Exploration
- Estimating Execution Time using Discrete-event Simulation for large complex Aerospace Systems
- Fine-Grained Performance and Power Analysis
- Selecting right processor for Next-Gen SoC
- Certification of IMA for Avionics System
- Incremental design issues in Avionics System
- Early system analysis of AVB based Systems
- Multi-core, Power Optimization- All about system design and exploration
- Modeling of Software Process using VisualSim Architect
- Linking System-level modeling to RTL and Source code
- Integrated Vehicle Health Management(IVHM) system development using VisualSim Architect
- ESL and IC-only Solutions are not the same
- System-level Models- How well do they correlate with the implementation?
- SSD and Power Reduction
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